IP Library Granted Patent US 9,177,863
Granted Patent B2
US 9,177,863 · App. 13/951,132 · Granted Nov 3, 2015

Multi-chip package with offset die stacking and method of making same

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Quick Facts
Patent No.
US 9,177,863
App. No.
13/951,132
Granted
Nov 3, 2015
Kind
B2
Abstract

A semiconductor device has a plurality of stacked semiconductor dice mounted on a substrate. Each die has similar dimensions. Each die has a first plurality of bonding pads arranged along a bonding edge of the die. A first group of the dice are mounted to the substrate with the bonding edge oriented in a first direction. A second group of the dice are mounted to the substrate with the bonding edge oriented in a second direction opposite the first direction. Each die is laterally offset in the second direction relative to the remaining dice by a respective lateral offset distance such that the bonding pads of each die are not disposed between the substrate and any portion of the remaining dice in a direction perpendicular to the substrate. A plurality of bonding wires connects the bonding pads to the substrate. A method of manufacturing a semiconductor device is also disclosed.

Claims (31)

1. A method of manufacturing a semiconductor device, comprising:

providing a substrate having a plurality of electrical connections;

mounting a first semiconductor die from a first group of semiconductor dice to the substrate such that a first plurality of bonding pads arranged along a first bonding edge of the first semiconductor die is oriented to face in a first direction;

mounting the remaining semiconductor dice from the first group of semiconductor dice to the substrate such that:

a first plurality of bonding pads arranged along a first bonding edge of each of the first group of semiconductor dice is oriented to face in the first direction; and

each remaining semiconductor die of the first group of semiconductor dice is laterally offset relative to the first semiconductor die in a second direction opposite the first direction by a respective lateral offset distance;

mounting a second group of semiconductor dice, intermixed with or over the first group of semiconductor dice, to the substrate such that:

a first plurality of bonding pads arranged along a first bonding edge of each of the second group of semiconductor dice is oriented to face in the second direction; and

each semiconductor die of the second group of semiconductor dice is laterally offset relative to the first semiconductor die in the first direction by a respective lateral offset distance; and

connecting bond wires between the plurality of electrical connections of the substrate and the respective bonding pads of the first and second groups of semiconductor dice after mounting the first and second groups of semiconductor dice to the substrate.

2. The method of claim 1 , wherein:

the respective lateral offset distance of each of the semiconductor dice is selected such that the bonding pads of each semiconductor die are not disposed between the substrate and any portion of the remaining semiconductor dice in a direction perpendicular to the substrate.

3. The method of claim 2 , wherein:

the first group of semiconductor dice comprises m semiconductor dice;

the second group of semiconductor dice comprises n semiconductor dice;

the mounting the remaining semiconductor dice from the first group of semiconductor semiconductor dice is performed such that the lateral offset distance Δ i , of an ith semiconductor die from the substrate of the first group of semiconductor dice is Δ i ,=(i−l)d; and

the mounting the second group of semiconductor dice is performed such that the lateral offset distance Δ j , of a jth semiconductor die from the substrate of the second group of semiconductor dice is Δ j ,=[m+(n−j)]d, where d is a predetermined distance.

4. The semiconductor device of claim 3 , wherein d is a lateral width of the first plurality of bonding pads of each semiconductor die in the second direction.

5. The method of claim 3 , wherein the mounting the first and second groups of semiconductor dice to the substrate comprises alternately mounting a semiconductor die from the first group and mounting a semiconductor die from the second group.

6. The method of claim 3 , wherein the mounting first and second groups of semiconductor dice to the substrate comprises mounting the semiconductor dice with bonding edges in alternating orientations, such that each semiconductor die is adjacent only to semiconductor dice having bonding edges in the opposite orientation.

7. The method of claim 3 , further comprising:

mounting a third group of semiconductor dice to the substrate such that:

a first plurality of bonding pads arranged along a first bonding edge of each of the third group of semiconductor dice is oriented to face in a third direction distinct from the first and second directions; and

each semiconductor die of the third group of semiconductor dice other than the a first semiconductor die of the third group is laterally offset relative to the first semiconductor die of the third group in a fourth direction opposite the third direction by a respective lateral offset distance; and

mounting a fourth group of semiconductor dice to the substrate such that:

a first plurality of bonding pads arranged along a first bonding edge of each of the second group of semiconductor dice is oriented to face in the fourth direction; and

each semiconductor die of the fourth group of semiconductor dice is laterally offset in the fourth direction by a respective lateral offset distance relative to the one of the third group of semiconductor dice closest to the substrate;

wherein:

the connecting bond wires further comprises connecting bond wires between additional electrical connections of the substrate and the respective bonding pads of the third and fourth groups of semiconductor dice; and

the connecting the bond wires is performed after mounting the third and fourth groups of semiconductor dice to the substrate.

8. The method of claim 3 , wherein the third and fourth directions are oriented at 90 degrees relative to the first and second directions.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 6, 2020
From: CPPIB CREDIT INVESTMENTS INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 054341/0057 →
RELEASE OF U.S. PATENT AGREEMENT (FOR NON-U.S. GRANTORS) Recorded Oct 12, 2018
From: ROYAL BANK OF CANADA, AS LENDER
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 047645/0424 →
AMENDED AND RESTATED U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) Recorded Aug 22, 2018
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CPPIB CREDIT INVESTMENTS, INC.
Reel/Frame 046900/0136 →
U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) Recorded Sep 9, 2014
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CPPIB CREDIT INVESTMENTS INC., AS LENDER; ROYAL BANK OF CANADA, AS LENDER
Reel/Frame 033706/0367 →
CHANGE OF ADDRESS Recorded Sep 3, 2014
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 033678/0096 →
CHANGE OF NAME Recorded Mar 13, 2014
From: MOSAID TECHNOLOGIES INCORPORATED
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 032439/0638 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2013
From: GILLINGHAM, PETER
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 030879/0635 →