Non-volatile semiconductor memory having multiple external power supplies
View Patent ↗A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.
1. A method for controlling a NAND flash memory device, the method comprising:
providing a first power supply voltage to a first power input pin of the NAND flash memory device;
providing a second power supply voltage to a second power input pin of the NAND flash memory device, the second power supply voltage being greater than the first power supply voltage;
accessing a first register of the NAND flash memory device to determine whether the NAND flash memory device supports the second power supply voltage;
setting a second register of the NAND flash memory device to select the second power supply voltage for generating a plurality of internal voltages in the NAND flash memory device; and
operating the NAND flash memory device for one of page program operation and block erase operation.
2. The method of claim 1 , wherein the setting the second register is performed only if the first register indicates that the NAND flash memory device supports the second power supply voltage.
3. The method of claim 1 , wherein the setting the second register includes a writing a logic 1 to a least significant bit of the second register to select the second power supply voltage for generating the plurality of internal voltages in the NAND flash memory device.
4. The method of claim 3 , further comprising;
clearing the second register of the NAND flash memory device by writing a logic 0 to the least significant bit of the second register to select the first power supply voltage instead of the second power supply voltage for generating the plurality of internal voltages in the NAND flash memory device.
5. The method of claim 1 , wherein the accessing the first register comprises checking a specific bit of the first register containing a logic 1 for indicating the NAND flash memory device supports the second power supply voltage.
6. The method as in claim 1 , wherein the plurality of internal voltages include a first internal voltage and a second internal voltage, the second internal voltage being greater than the first internal voltage.
7. The method of claim 1 further comprising:
providing one or more power source configured to supply the first power supply voltage and the second power supply voltage to the NAND flash memory device.
8. The method as in claim 1 , wherein the plurality of internal voltages are page program voltage and block erase voltage.
9. The method of claim 1 , wherein the first power supply voltage is 3.3V and the second power supply voltage is 12V.
10. The method of claim 1 , wherein each of the plurality of internal voltages is greater than the second power supply voltage.
11. A non-volatile memory system comprising:
a first power supply voltage;
a second power supply voltage being greater than the first power supply voltage;
a memory device, the memory device comprising:
a NAND flash memory configured to store data,
a first power input pin configured to receive the first power supply voltage for operating the memory device,
a second power input pin configured to receive the second power supply voltage,
a power management circuitry configured to generate plurality of internal voltages from at least one of the first power supply voltage and the second power supply voltage, the plurality of internal voltages configured to be utilized by the NAND flash memory,
a first register configured to indicate whether the memory device supports the second power supply voltage, and
a second register configured to be set for enabling the second power supply voltage; and
a memory controller communicatively coupled to the memory device and configured to read a value of the first register of the memory device, and enable a bit of the second register of the memory device to enable utilization of the second power supply voltage for generating the plurality of internal voltages by the power management circuitry of the memory device when the value read from the first register of the memory device indicates that the memory device supports the second power supply.
12. The non-volatile memory system of claim 11 , wherein the second register comprises a plurality of bits and the memory controller is further configured to write a logic 1 to a least significant bit of the second register for enabling utilization of the second power supply voltage only if the first register indicates the memory device supports the second power supply voltage.
13. The non-volatile memory system of claim 11 , wherein the first register comprises a plurality of bits and a single bit of the first register is used for indicating whether the memory device supports the second power supply voltage.
14. The non-volatile memory system of claim 11 , wherein the first power supply voltage is 3.3V and the second power supply voltage is 12V.
15. The non-volatile memory system of claim 11 , wherein each of the plurality of internal voltages is greater than the second power supply voltage.
16. The non-volatile memory system of claim 11 , wherein the plurality of internal voltages are utilized for storing the data in the NAND flash memory.
17. The non-volatile memory system as in claim 16 , wherein the plurality of internal voltages comprise a page program voltage and a block erase voltage.
18. The non-volatile memory system of claim 11 , wherein the plurality of internal voltages include a first internal voltage and a second internal voltage, the second internal voltage being greater than the first internal voltage.
19. The non-volatile memory system of claim 11 further comprising:
one or more power source configured to provide the first power supply voltage and the second power supply voltage to the memory device.
20. The non-volatile memory system of claim 11 further comprising:
one or more power pins configured to convey the first power supply voltage and the second power supply voltage from an external power source to the memory device.