Non-volatile semiconductor memory having multiple external power supplies
View Patent ↗A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.
1. A NAND flash memory device comprising:
a NAND flash memory configured to store data;
I/O logic configured to enable access to the data in the NAND flash memory;
a first power input pin configured to receive an external Vcc power supply voltage;
a second power input pin configured to receive an external Vpp power supply voltage, the external Vpp power supply voltage being greater than the external Vcc power supply voltage;
a third power input pin configured to receive an external Vccq power supply voltage, the external Vccq power supply voltage powering the I/O logic;
a device information register configured to indicate whether the NAND flash memory device supports the external Vpp power supply voltage;
a device control register configured to enable the external Vpp power supply voltage via a configuration command; and
power management circuitry configured to convert the external Vpp power supply voltage into a plurality of internal voltages when the external Vpp power supply voltage is enabled by the device control register and convert the external Vcc power supply voltage into the plurality of internal voltages when the external Vpp power supply voltage is not enabled by the device control register, the plurality of internal voltages being of sufficient magnitude to permit a number of selectively differing voltage applications to cells of the NAND flash memory to enable at least one operation in relation to the data.
2. The NAND flash memory device as in claim 1 , wherein the device control register comprises a plurality of bits.
3. The NAND flash memory device as in claim 2 , wherein a single bit of the device control register is used for enabling the external Vpp power supply voltage.
4. The NAND flash memory device as in claim 1 , wherein the device information register comprises a plurality of bits.
5. The NAND flash memory device as in claim 4 , wherein a single bit of the device information register is used for indicating whether the NAND flash memory device supports the external Vpp power supply voltage.
6. The NAND flash memory device as in claim 1 , wherein each of the plurality of internal voltages is greater than the external Vpp power supply voltage.
7. The NAND flash memory device as in claim 1 , wherein the plurality of internal voltages includes a first internal voltage and a second internal voltage, the second internal voltage being greater than the first internal voltage.
8. The NAND flash memory device as in claim 1 , wherein the more than internal voltages conveyed to the NAND flash memory enable an operation for one of:
i) programming of cells in the NAND flash memory,
ii) erasing of cells in the NAND flash memory, and
iii) reading data from cells in the NAND flash memory.
9. The NAND flash memory device as in claim 1 further comprising switch circuitry configured to select between inputting the external Vcc power supply voltage and the external Vpp power supply voltage into the power management circuitry to generate the plurality of internal voltages.
10. The NAND flash memory device as in claim 1 , wherein the external Vcc power supply voltage is 3.3V and the external Vpp power supply voltage is 12V.
11. The NAND flash memory device as in claim 1 further comprising:
a substrate comprising:
a first conductive path for conveying the external Vcc power supply voltage from the first power input pin to the NAND flash memory and the power management circuitry,
a second conductive path for conveying the external Vpp power supply voltage from the second power input pin to the power management circuitry, and
multiple conductive paths for conveying the plurality of internal voltages from the power management circuitry to the NAND flash memory.
12. A memory system comprising:
a NAND flash memory device comprising:
a NAND flash memory configured to store data,
I/O logic configured to enable access to the data in the NAND flash memory,
a first power input pin configured to receive an external Vcc power supply voltage,
a second power input pin configured to receive an external Vpp power supply voltage, the external Vpp power supply voltage being greater than the external Vcc power supply voltage,
a third power input pin configured to receive an external Vccq power supply voltage, the external Vccq power supply voltage powering the I/O logic,
a device information register configured to indicate whether the NAND flash memory device supports the external Vpp power supply,
a device control register configured to enable the external Vpp power supply voltage via a configuration command, and
power management circuitry configured to convert the external Vpp power supply voltage into a plurality of internal voltages when the external Vpp power supply voltage is enabled by the device control register and circuitry convert the external Vcc power supply voltage into the plurality of internal voltages when the external Vpp power supply voltage is not enabled by the device control register, the plurality of internal voltages being of sufficient magnitude to permit a number of selectively differing voltage applications to cells of the NAND flash memory to enable at least one operation in relation to the data;
a controller configured to provide the configuration command to the NAND flash memory device for enabling the external Vpp power supply voltage; and
a power converter configured to provide the external Vcc power supply voltage and the external Vpp power supply voltage to the NAND flash memory device.
13. The memory system as in claim 12 , wherein size of the device control register comprises a plurality of bits.
14. The memory system as in claim 13 , wherein a single bit of the device control register is used for enabling the external Vpp power supply voltage.
15. The memory system as in claim 12 , wherein size of the device information register comprises a plurality of bits.
16. The memory system as in claim 15 , wherein a single bit of the device information register is used for indicating whether the NAND flash memory device supports the external Vpp power supply voltage.
17. The memory system as in claim 12 , wherein each of the plurality of internal voltages is greater than the external Vpp power supply voltage.
18. The memory system as in claim 12 , wherein the plurality of internal voltages includes a first internal voltage and a second internal voltage, the second internal voltage being greater than the first internal voltage.
19. The memory system as in claim 12 , wherein the plurality of internal voltages conveyed to the NAND flash memory enable an operation for one of:
i) programming of cells in the NAND flash memory,
ii) erasing of cells in the NAND flash memory, and
iii) reading data from cells in the NAND flash memory.
20. The memory system of claim 12 , further comprising switch circuitry configured to select between inputting the external Vcc power supply voltage and the external Vpp power supply voltage into the power management circuitry to generate the plurality of internal voltages.
21. The memory system of claim 12 , wherein the external Vcc power supply voltage is 3.3V and the external Vpp power supply voltage is 12V.
22. The memory system of claim 12 , wherein the NAND flash memory device further comprises:
a substrate comprising:
a first conductive path for conveying the external Vcc power supply voltage from the first power input pin to the NAND flash memory and the power management circuitry,
a second conductive path for conveying the external Vpp power supply voltage from the second power input pin to the power management circuitry, and
multiple conductive paths for conveying the plurality of internal voltages from the power management circuitry to the NAND flash memory.