Bridging device having a configurable virtual page size
A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. The bridge device has memory organized as banks, where each bank is configured to have a virtual page size that is less than the maximum physical size of the page buffer. Therefore only a segment of data corresponding to the virtual page size stored in the page buffer is transferred to the bank. The virtual page size of the banks is provided in a virtual page size (VPS) configuration command having an ordered structure where the position of VPS data fields containing VPS configuration codes in the command correspond to different banks which are ordered from a least significant bank to a most significant bank. The VPS configuration command is variable in size, and includes only the VPS configuration codes for the highest significant bank being configured and the lower significant banks.
1. A composite memory device configured in a multi-chip-package (MCP), the composite memory device comprising:
a plurality of discrete NAND flash memory dies, each discrete NAND flash memory die comprising at least two memory planes, a respective page buffer for each memory plane, and a NAND flash memory interface for the NAND flash memory die; and
a bridge device coupled to the plurality of discrete NAND flash memory dies, the bridge device comprising:
a bridge chip I/O interface for communicating with a memory controller and receiving a command in a first format and data in the first format;
a command format converter for converting the command from the first format to a second format, the second format being a format for the NAND flash memory dies;
a data format converter configured to convert the data from the first format to the second format;
a plurality of bridge chip memory device interfaces, each bridge chip memory device interface coupled to the NAND flash memory interface of the corresponding one of plurality of discrete NAND flash memory dies and configured to receive the command in the second format and the data in the second format;
a plurality of virtual page buffers, each virtual page buffer corresponding to one memory plane of the plurality of discrete NAND flash memory dies and having a configurable page buffer size that is equal or less than the maximum size of the respective page buffer of the corresponding memory plane; and
a virtual page size configurator configured to latch virtual page size configuration codes from the bridge chip I/O interface at different time periods, each of the page size configuration codes received at one of the different time periods corresponding to a different discrete NAND flash memory die.
2. The composite memory device of claim 1 , wherein a format of the bridge chip I/O interface differs from a format of the plurality of first memory interfaces.
3. The composite memory device of claim 1 , wherein a format of the bridge chip I/O interface is the same as a format of the plurality of first memory interfaces.
4. The composite memory device of claim 1 , wherein the different time periods correspond to clock cycles.
5. The composite memory device of claim 4 , wherein the virtual page size configurator comprises registers, each register comprising an input coupled to the bridge chip I/O interface and configured to latch the virtual page size configuration codes in response to pulsed signals received at different clock cycles.
6. The composite memory device of claim 5 , wherein the virtual page size configurator further comprises domino activation logic configured to generate the pulsed signals in response to one of rising and falling edges of a clock signal.
7. The composite memory device of claim 6 , wherein the domino activation logic comprises a plurality of latch signal generators arranged in series and configured to be enabled in sequence for generating the pulsed signals in response to one of the rising and falling edges of the clock signal.
8. The composite memory device of claim 7 , wherein the domino activation logic further comprises a seed signal generator configured to enable a first latch signal generator of the plurality of latch signal generators in response to a starting signal.
9. The composite memory device of claim 8 , wherein at least one of the plurality of latch signal generators is configured to enable a subsequent latch signal generator after a corresponding pulsed signal is generated.