Nonvolatile memory with split substrate select gates and hierarchical bitline configuration
View Patent ↗Generally, the present disclosure provides a non-volatile memory device having a hierarchical bitline structure for preventing erase voltages applied to one group of memory cells of the memory array from leaking to other groups in which erasure is not required. Local bitlines are coupled to the memory cells of each group of memory cells. Each local bitline can be selectively connected to a global bitline during read operations for the selected group, and all the local bitlines can be disconnected from the global bitline during an erase operation when a specific group is selected for erasure. Select devices for electrically connecting each bitline of a specific group of memory cells to the global bitline have device bodies that are electrically isolated from the bodies of those memory cells.
1. A non-volatile memory comprising:
at least two groups of non-volatile memory cells each eraseable in an erase operation;
local bitlines coupled to the non-volatile memory cells of each group of the at least two groups;
a global bitline; and
a plurality of select devices corresponding to a group of the at least two groups, the plurality of select devices configured to disconnect all the local bitlines of the group from the global bitline, wherein each of the plurality of select devices corresponding to the group are disabled in response to receiving a local bitline select signal.
2. The non-volatile memory of claim 1 , wherein a body of a select device of the plurality of select devices for electrically connecting a local bitline coupled to the non-volatile memory cells of one group of the at least two groups to the global bitline, is electrically isolated from bodies of the non-volatile memory cells of the one group.
3. The non-volatile memory of claim 2 , wherein the non-volatile memory cells are arranged as NAND cell strings.
4. The non-volatile memory of claim 3 , wherein each of the at least two groups of non-volatile memory cells are formed in corresponding pocket wells of a substrate and are electrically isolated from each other.
5. The non-volatile memory of claim 4 , wherein each of the corresponding pocket wells is connected to a local erase line for receiving an erase voltage.
6. The non-volatile memory of claim 5 , wherein the select device is formed in a region of the substrate external to the pocket wells.
7. The non-volatile memory of claim 6 , wherein the pocket wells have a first dopant type and are formed in a well having a second dopant type, the well being formed in the substrate having the first dopant type.
8. The non-volatile memory of claim 7 , wherein the first dopant type is p-type and the second dopant type is n-type.
9. The non-volatile memory of claim 6 , wherein the NAND cell strings comprise planar NAND cell strings.
10. The non-volatile memory of claim 6 , wherein the NAND cell strings comprise three-dimension (3D) stacked NAND cell strings having a body with a vertical channel electrically coupled to a respective pocket well.
11. The non-volatile memory of claim 6 , wherein a first select device corresponding to a first group of the at least two groups and a second select device corresponding to a second group of the at least two groups are formed adjacent to each other in the substrate and share a single contact to the global bit line.
12. The non-volatile memory of claim 3 , wherein the NAND cell strings comprise 3D stacked NAND cell strings having bodies electrically isolated from a substrate.
13. The non-volatile memory of claim 12 , wherein the plurality of select devices corresponding to each of the at least two groups are formed in the substrate.
14. The non-volatile memory of claim 13 , wherein a source line is formed in the substrate and electrically isolates the bodies from the substrate.
15. The non-volatile memory of claim 14 , wherein the bodies have a first dopant type, the source line has a second dopant type, and the substrate has the first dopant type.
16. The non-volatile memory of claim 15 , wherein the first dopant type is p-type and the second dopant type is n-type.
17. The non-volatile memory of claim 13 , wherein the source line is formed as a conductive line over the substrate.
18. The non-volatile memory of claim 13 , wherein a first select device corresponding to a first group of the at least two groups and a second select device corresponding to a second group of the at least two groups are formed adjacent to each other in the substrate and share a single contact to the global bit line.
19. The non-volatile memory of claim 3 , wherein each of the at least two groups includes at least two NAND memory blocks of NAND cell strings.
20. The non-volatile memory of claim 1 , wherein each of the plurality of select devices corresponding to the group includes a pass transistor enabled by the local bitline select signal.
21. The non-volatile memory of claim 20 , further including row decoding circuitry configured to provide the local bitline select signal corresponding to each pass transistor for disconnecting all the local bitlines from the global bitline in an erase operation.
22. The non-volatile memory of claim 1 , wherein each of the at least two groups of non-volatile memory cells are formed in corresponding pocket wells of a substrate and are electrically isolated from each other, and wherein a body of a select device of the plurality of select devices is formed in a region of the substrate external to the pocket wells.