IP Library Granted Patent US 8,711,573
Granted Patent B2
US 8,711,573 · App. 13/777,645 · Granted Apr 29, 2014

Using interrupted through-silicon-vias in integrated circuits adapted for stacking

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Quick Facts
Patent No.
US 8,711,573
App. No.
13/777,645
Granted
Apr 29, 2014
Kind
B2
Abstract

In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack.

Claims (17)

1. A method of selecting a semiconductor device in a stack of semiconductor devices, comprising:

providing logic levels to a first plurality of serial through silicon via (TSV) inputs on a first device in a stack;

within the first device, receiving the logic levels on the first plurality of TSV inputs, scrambling the received logic levels, and providing the scrambled received logic levels to a first plurality of TSV outputs connected to a first plurality of serial TSV inputs on a second device in the stack;

within the second device, receiving the logic levels on the first plurality of TSV inputs, scrambling the received logic levels, and providing the scrambled received logic levels to a first plurality of TSV outputs connected to a first plurality of serial TSV inputs on a third device in the stack;

within the third device, receiving the logic levels on the first plurality of TSV inputs; and

using the received logic levels in each of the first, second, and third devices to select one of the first, second, or third devices.

2. The method of selecting a semiconductor device as claimed in claim 1 where the first, second, and third devices are identical.

3. The method of selecting a semiconductor device as claimed in claim 1 where the serial TSV outputs on each of the devices are located on the same axis perpendicular to the surface of the device as the corresponding TSV inputs.

4. The method of selecting a semiconductor device as claimed in claim 1 where the serial TSV outputs are located on an axis perpendicular to the surface of the device rotated 180° about the center of the device from an axis perpendicular to the surface of the device of the corresponding TSV inputs.

5. The method of selecting a semiconductor device as claimed in claim 1 where the scrambling comprises connecting a logic level received on a first serial TSV input to a second serial TSV output and connecting a logic level received on a second serial TSV input to a third serial TSV output.

6. The method of selecting a semiconductor device as claimed in claim 5 where the first serial TSV input of the first device receives a first logic level and second serial TSV input of the first device receives a second logic level opposite the first logic level.

7. The method of selecting a semiconductor device as claimed in claim 6 where the received logic levels in each of the first, second, and third devices are scrambled to form a thermometer code.

8. The method of selecting a semiconductor device as claimed in claim 1 where the serial TSV inputs are directly connected to serial TSV outputs within each device.

9. The method of selecting a semiconductor device as claimed in claim 1 where received logic levels in each of the first, second, and third devices represent the position of the device in a stack of devices.

10. The method of selecting a semiconductor device as claimed in claim 9 where received logic levels in each of the first, second, and third devices are encoded to provide a device ID.

11. The method of selecting a semiconductor device as claimed in claim 9 further comprising the steps of providing a command including a device address, and comparing the device address to the logic level within each of the first, second, and third devices to determine which device should execute the command.

12. The method of selecting a semiconductor device as claimed in claim 11 where only a single device executes the command.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING PARTY'S NAME PREVIOUSLY RECORDED AT REEL: 058297 FRAME: 0458. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Aug 30, 2023
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 064761/0349 →
CHANGE OF NAME Recorded Oct 19, 2021
From: CONVERSANT INTELLECTUAL PROPERTY INC.
To: MOSAID TECHNOLOGIES INCORPORATED
Reel/Frame 058297/0458 →
RELEASE OF SECURITY INTEREST Recorded Nov 6, 2020
From: CPPIB CREDIT INVESTMENTS INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 054341/0057 →
RELEASE OF U.S. PATENT AGREEMENT (FOR NON-U.S. GRANTORS) Recorded Oct 12, 2018
From: ROYAL BANK OF CANADA, AS LENDER
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 047645/0424 →
AMENDED AND RESTATED U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) Recorded Aug 22, 2018
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CPPIB CREDIT INVESTMENTS, INC.
Reel/Frame 046900/0136 →
U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) Recorded Sep 9, 2014
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CPPIB CREDIT INVESTMENTS INC., AS LENDER; ROYAL BANK OF CANADA, AS LENDER
Reel/Frame 033706/0367 →
CHANGE OF ADDRESS Recorded Sep 3, 2014
From: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 033678/0096 →
CHANGE OF NAME Recorded Mar 13, 2014
From: MOSAID TECHNOLOGIES INCORPORATED
To: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
Reel/Frame 032439/0638 →