Multi-controller write operations
View Patent ↗A system and method for high performance multi-controller processing is disclosed. Independent Network storage controllers (NSCs) are connected by a high-speed data link. The NSCs control a plurality of storage devices. connected by a Fiber Channel Arbitrated Loop (FCAL). To provide redundancy, for a given logical unit of storage one NSC will function as the primary controller and the other NSC will function as the primary controller and the enhance the efficiency of command-response data transfers between NSCs, mirror memory is correlated with primary memory and named resources are used for command-response data transfers. Methods are disclosed to provide for efficient active mirroring of data.
1. A method of processing a write operation in a multi-controller processing environment wherein the write operation comprises a SCSI write command, comprising:
receiving, at a primary storage controller, a request for a write operation;
allocating a block of cache memory in the primary storage controller;
receiving, in the primary storage controller, data associated with the write operation;
reserving bandwidth on a communication link between the primary storage controller and a mirror controller for command response packets; and
transmitting the command response packets on the reserved bandwidth; and
transmitting the data from the primary storage controller to a corresponding block of cache memory in a mirror storage controller via the communication link, by:
allocating a host transfer block in the primary storage controller;
writing data associated with the write operation to the host transfer block; and
posting the host transfer block to a data flow queue;
generating, in the primary storage controller, a scatter gather list data structure in resnonse to the write operation;
allocating a fiber exchange descriptor;
associating a scatter gather list with a redundant invalid entry managed by the primary storage controller;
associating the scatter gather list with a redundant invalid entry on the mirror storage controller; and
associating the scatter gather list with a specific mirror node on the mirror storage controller.
2. The method of claim 1 , wherein reserving bandwidth on a communication link between the primary storage controller and a mirror storage controller for command response packets comprises reserving positions on a serial communication link between the primary storage controller and the mirror storage controller.
3. The method of claim 1 , wherein transmitting the data from the primary storage controller to a corresponding block of cache memory in a mirror storage controller via the communiction link comprises:
issuing a request read message from the primary storage controller which contains data identifying a logical unit associated with the data, a starting virtual block address, a redundant invalid entry index, and at least one buffer address; and
storing an address for the host transfer block in an array indexed by the redundant invalid entry index.
4. The method of claim 3 , further comprising:
receiving, at the mirror storage controller, the request read message from the primary storage controller;
storing context information associated with the write operation in the mirror node associated with the redundant invalid entry index;
constructing, in the mirror storage controller, a mirror scatter gather list; and
transmitting a ready to receive message to the primary storage controller.
5. The method of claim 4 , further comprising:
receiving the data associated with the write command in the mirror storage controller;
updating the redundant invalid entry index; and
releasing the scatter gather list.
6. A computer program product comprising logic instructions stored on a computer-readable storage medium which, when executed by a processor, configure the processor to process a write operation in a multi-controller processing environment wherein the write operation comprises a SCSI write command by executing operations comprising:
receiving, at a primary storage controller, a request for a write operation;
allocating a block of cache memory in the primary storage controller;
receiving, in the primary storage controller, data associated with the write operation;
reserving bandwidth on a communication link between the primary storage controller and a mirror storage controller for command response packets;
transmitting the command response packets on the reserved bandwidth; and
transmitting the data from the primary storage controller to a corresponding block of cache memory in the mirror storage controller via the communication link, by:
allocating a host transfer block in the primary storage controller;
writing data associated with the write operation to the host transfer block; and
posting the host transfer block to a data flow queue;
generating, in the primary storage controller, a scatter gather list data structure in resnonse to the write operation;
allocating a fiber exchange descriptor;
associating a scatter gather list with a redundant invalid entry managed by the primary storage controller;
associating the scatter gather list with a redundant invalid entry on the mirror storage controller; and
associating the scatter gather list with a specific mirror node on the mirror storage controller.
7. The computer program product of claim 6 , wherein reserving bandwidth on a communication link between the primary storage controller and a mirror controller for command response packets comprises reserving positions on a serial communication link between the primary storage controller and the mirror storage controller.
8. The computer program product of claim 6 , wherein transmitting the data from the primary storage controller to a corresponding block of cache memory in a mirror storage controller via the communication link comprises:
issuing a request read message from the primary storage controller which contains data identifying a logical unit associated with the data, a starting virtual block address, a redundant invalid entry index, and at least one buffer address; and
storing an address for the host transfer block in an array indexed by the redundant invalid entry index.
9. The computer program product of claim 8 , further comprising:
receiving, at the mirror storage controller, the request read message from the primary storage controller;
storing context information associated with the write operation in the mirror node associated with the redundant invalid entry index;
constructing, in the mirror storage controller, a mirror scatter gather list; and
transmitting a ready to receive message to the primary storage controller.
10. The computer program product of claim 9 , further comprising:
receiving the data associated with the write command in the mirror storage controller;
updating the redundant invilid entry index; and
releasing the scatter gather list.
11. A storage controller, comprising:
a first port to receive a write operation from a host computer wherein the write operation comprises a SCSI write command;
a second port to interface to one or more storage devices;
a processor;
a memory module connected to the processor and comprising logic instructions stored on a computer-readable storage medium which, when executed by the processor, configure the processor to:
allocate a block of cache memory in the primary storage controller;
receive, in the storage controller, data associated with the write operation;
reserve bandwidth on a communication link between the primary storage controller and a second storage controller for command response packets;
transmit the command response packets on the reserved bandwidth; and
transmit the data from the storage controller to a corresponding block of cache memory in a the second storage controller via the communication link, by:
allocating a host transfer block in the primary storage controller;
writing data associated with the write operation to the host transfer block; and
posting the host transfer block to a data flow queue;
generate, in the primary storage controller, a scatter gather list data structure in resnonse to the write operation;
allocate a fiber exchange descriptor;
associate a scatter gather list with a redundant invalid entry managed by the primary storage controller;
associate the scatter gather list with a redundant invalid entry on the second storage controller; and
associate the scatter gather list with a specific mirror node on the second storage controller.
12. The storage controller of claim 11 , wherein the memory module further comprises logic instructions which, when executed by the processor, cause the processor to reserve positions on a serial communication link between the storage controller and the second storage controller.
13. The storage controller of claim 11 , wherein the memory module further comprises logic instructions which, when executed by the processor, cause the processor to:
issue a request read message from the storage controller which contains data identifying a logical unit associated with the data, a starting virtual block address, a redundant invalid entry index, and at least one buffer address; and
store an address for the host transfer block in an array indexed by the redundant invalid entry index.
14. The storage controller of claim 13 , wherein the memory module further comprises logic instructions which, when executed by the processor, cause the processor to:
receive, at the second storage controller, the request read message from the primary controller;
store context information associated with the write operation in the mirror node associated with the redundant invalid entry index;
construct, in the second storage controller, a mirror scatter gather list; and
transmit a ready to receive message to the primary controller.