NAND flash architecture with multi-level row decoding
View Patent ↗A NAND flash memory device is disclosed. The NAND flash memory device includes a NAND flash memory array defined as a plurality of sectors. Row decoding is performed in two levels. The first level is performed that is applicable to all of the sectors. This can be used to select a block, for example. The second level is performed for a particular sector, to select a page within a block in the particular sector, for example. Read and program operations take place to the resolution of a page within a sector, while erase operation takes place to the resolution of a block within a sector.
1. A method for performing mutli-level row decoding in a NAND flash memory core, the NAND flash memory core including a plurality of memory cell array sectors and a plurality of blocks, each of the plurality of blocks being divided into portions each belonging to one of the plurality of memory cell array sectors, the method comprising:
performing, using a global row decoder, a first level of row decoding to select a block spanning the plurality of memory cell array sectors; and
performing, using a first local row decoder associated with a first memory cell array sector of the plurality of memory cell array sectors, a second level of row decoding to select a page within the selected block and the first memory cell array sector.
2. The method of claim 1 , wherein the second level of row decoding further comprises selecting, using a second local row decoder associated with a second memory cell array sector of the plurality of memory cell array sectors, an additional page within the selected block and the second memory cell array sector, the selection of the additional page being performed in parallel with the selection of the page.
3. The method of claim 1 wherein:
each memory cell array sector of the plurality of memory cell array sectors includes wordlines and a cell substrate; and
all wordlines and cell substrates of memory cell array sectors for which a page has not been selected are biased to a common voltage.
4. The method of claim 3 wherein the common voltage is substantially 0V.
5. The method of claim 1 , wherein the plurality of memory cell array sectors comprise at least four memory cell array sectors.
6. The method of claim 1 , wherein:
the first memory cell array sector includes a plurality of columns and a plurality of rows; and
the second level of row decoding comprises transferring contents of a page buffer circuit of the NAND flash memory core to a selected row of the first memory cell array sector.