Device selection schemes in multi chip package NAND flash memory system
View Patent ↗Systems and methods are provided for perform device selection in multi-chip package NAND flash memory systems. In some embodiments, the memory controller performs device selection by command. In other embodiments, the memory controller performs device selection by input address.
1. A memory system comprising:
a memory controller;
a plurality of memory devices connected to the controller via a common bus with a multi-drop connection;
wherein the memory controller performs device selection by input address;
each memory device comprising:
a register containing a device identifier;
a device identifier comparator that compares selected bits of a received input address to contents of the register to determine if there is a match, and wherein a given device is selected if the device identifier comparator of the given device determines there is a match;
wherein each memory device further comprises a burst data controller that causes the memory device to be selected:
when the device identifier comparator determines there is a match;
while a command input is in progress; and
while an address input is in progress.
2. The memory system of claim 1 comprising:
a global buffer in which command, data and input address are initially stored upon receipt;
wherein the device identifier comparator obtains the selected bits of the received input address via the global buffer.
3. The memory system of claim 1 wherein in each memory device, the burst data controller comprises an output that indicates whether the memory device is selected or deselected.
4. The memory system of claim 1 wherein each burst data controller comprises:
a logic circuit that receives an output of the device identifier comparator, an address latch enable signal that indicates whether an address input is in progress, and a command latch enable signal that indicates whether a command input is in progress, and wherein the logic circuit generates an output that indicates whether the memory device is selected or deselected.
5. A memory system comprising:
a memory controller;
a plurality of memory devices connected to the controller via a common bus with a multi-drop connection;
wherein the memory controller performs device selection by input address;
each memory device comprising:
a register containing a device identifier;
a device identifier comparator that compares selected bits of a received input address to contents of the register to determine if there is a match, and wherein a given device is selected if the device identifier comparator of the given device determines there is a match
wherein each memory device further comprises:
a write enable buffer for buffering a received write enable signal, the write buffer having an input for receiving an indication of whether that memory device is selected or deselected, and wherein the write enable buffer is disabled when the memory device is deselected;
a read enable buffer for buffering a received read enable signal, the read buffer having an input for receiving an indication of whether that memory device is selected or deselected, and wherein the read enable buffer is disabled when the memory device is deselected.
6. The memory system of claim 1 wherein device selection is performed by input address with device interleave operations.
7. The memory system of claim 6 wherein the interleave operation comprises one of:
page program of a first device interleaved with page program of a second device;
page program of a first device interleaved with page read of a second device;
page read of a first device interleaved with page read of a second device.
8. The memory system of claim 1 wherein the plurality of devices comprises a plurality of NAND flash devices that are part of a multi-chip package.
9. The memory system of claim 8 comprising:
a common chip enable for the plurality of NAND flash devices.
10. A memory system comprising:
a memory controller;
a plurality of memory devices connected to the controller via a common bus with a multi-drop connection;
wherein the memory controller performs device selection by input address;
each memory device comprising:
a register containing a device identifier;
a device identifier comparator that compares selected bits of a received input address to contents of the register to determine if there is a match, and wherein a given device is selected if the device identifier comparator of the given device determines there is a match;
wherein the common bus comprises:
a write protect line;
a write enable line;
a read enable line;
an address latch enable line;
a command latch enable line;
a chip enable line;
an I/O for command, address and data; and
a ready/busy line.
11. A memory device for use in memory system comprising a memory controller, and a plurality of memory devices inclusive of the memory device connected to the controller via a common bus with a multi-drop connection, the memory device comprising:
a register containing a device identifier;
a device identifier comparator that compares selected bits of a received input address to contents of the register to determine if there is a match, and wherein the memory device is selected if the device identifier comparator determines there is a match;
a burst data controller that causes the memory device to be selected:
when the device identifier comparator determines there is a match;
while a command input is in progress; and
while an address input is in progress.
12. The memory device of claim 11 comprising:
a global buffer in which command, data and input address are initially stored upon receipt
wherein the device identifier comparator obtains the selected bits of the received input address via the global buffer.
13. The memory device of claim 11 wherein the burst data controller comprises an output that indicates whether the memory device is selected or deselected.
14. The memory device of claim 11 wherein the burst data controller comprises:
a logic circuit that receives an output of the device identifier comparator, an address latch enable signal that indicates whether an address input is in progress, and a command latch enable signal that indicates whether a command input is in progress, and wherein the logic circuit generates an output that indicates whether the memory device is selected or deselected.
15. A memory device for use in memory system comprising a memory controller, and a plurality of memory devices inclusive of the memory device connected to the controller via a common bus with a multi-drop connection, the memory device comprising:
a register containing a device identifier;
a device identifier comparator that compares selected bits of a received input address to contents of the register to determine if there is a match, and wherein the memory device is selected if the device identifier comparator determines there is a match;
wherein the memory device further comprises:
a write enable buffer for buffering a received write enable signal, the write buffer having an input for receiving an indication of whether that memory device is selected or deselected, and wherein the write enable buffer is disabled when the memory device is deselected;
a read enable buffer for buffering a received read enable signal, the read buffer having an input for receiving an indication of whether that memory device is selected or deselected, and wherein the read enable buffer is disabled when the memory device is deselected.
16. The memory device of claim 11 wherein device selection is performed by input address with device interleave operations.
17. The memory device of claim 16 wherein the interleave operation comprises one of:
page program of the memory device interleaved with page program of a second device;
page program of the memory device interleaved with page read of a second device;
page read of the memory device interleaved with page read of a second device.
18. The memory device of claim 11 wherein the plurality of devices comprises a plurality of NAND flash devices that are part of a multi-chip package.
19. The memory device of claim 18 comprising:
a common chip enable for the plurality of NAND flash devices.
20. A memory device for use in memory system comprising a memory controller, and a plurality of memory devices inclusive of the memory device connected to the controller via a common bus with a multi-drop connection, the memory device comprising:
a register containing a device identifier;
a device identifier comparator that compares selected bits of a received input address to contents of the register to determine if there is a match, and wherein the memory device is selected if the device identifier comparator determines there is a match;
wherein the common bus comprises:
a write protect line;
a write enable line;
a read enable line;
an address latch enable line;
a command latch enable line;
a chip enable line;
an I/O for command, address and data; and
a ready/busy line.
21. A method for use in a memory system comprising a memory controller and a plurality of memory devices connected to the controller via a common bus with a multi-drop connection, the method comprising:
the memory controller performing device selection by input address;
each memory device maintaining a device identifier in a register;
a device identifier comparator in each memory device comparing selected bits of a received input address to contents of the register of the memory device to determine if there is a match, and wherein a given device is selected if the device identifier comparator of the given device determines there is a match;
a burst data controller in each memory device causing the memory device to be selected:
when the device identifier comparator determines there is a match;
while a command input is in progress; and
while an address input is in progress.
22. The method of claim 21 comprising:
each memory device Initially storing command, data and input address are initially stored upon receipt in a global buffer
wherein in each memory device the device identifier comparator obtains the selected bits of the received input address via the global buffer.
23. The method of claim 21 wherein in each memory device, the burst data controller generating an output that indicates whether the memory device is selected or deselected.
24. The method of claim 21 further comprising, in each memory device:
in the burst data controller of the memory device:
a) receiving in a logic circuit an output of the device identifier comparator of the memory device;
b) generating an address latch enable signal that indicates whether an address input is in progress,
c) generating a command latch enable signal that indicates whether a command input is in progress,
the method further comprising the logic circuit generating an output that indicates
whether the memory device is selected or deselected.
25. A method for use in a memory system comprising a memory controller and a plurality of memory devices connected to the controller via a common bus with a multi-drop connection, the method comprising:
the memory controller performing device selection by input address;
each memory device maintaining a device identifier in a register;
a device identifier comparator in each memory device comparing selected bits of a received input address to contents of the register of the memory device to determine if there is a match, and wherein a given device is selected if the device identifier comparator of the given device determines there is a match;
the method further comprising, in each memory device:
buffering a received write enable signal in a write buffer, the write buffer having an input for receiving an indication of whether that memory device is selected or deselected, and wherein the write enable buffer is disabled when the memory device is deselected;
for buffering a received read enable signal in a read buffer, the read buffer having an input for receiving an indication of whether that memory device is selected or deselected, and wherein the read enable buffer is disabled when the memory device is deselected.
26. The method of claim 21 wherein device selection is performed by input address with device interleave operations.
27. The method of claim 26 wherein the interleave operation comprises one of:
page program of a first device interleaved with page program of a second device;
page program of a first device interleaved with page read of a second device;
page read of a first device interleaved with page read of a second device.
28. The method of claim 21 wherein the plurality of devices comprises a plurality of NAND flash devices that are part of a multi-chip package.
29. The method of claim 28 further comprising using a common chip enable for the plurality of NAND flash devices.
30. A method for use in a memory system comprising a memory controller and a plurality of memory devices connected to the controller via a common bus with a multi-drop connection, the method comprising:
the memory controller performing device selection by input address;
each memory device maintaining a device identifier in a register;
a device identifier comparator in each memory device comparing selected bits of a received input address to contents of the register of the memory device to determine if there is a match, and wherein a given device is selected if the device identifier comparator of the given device determines there is a match;
the method further comprising using a common bus comprising:
a write protect line;
a write enable line;
a read enable line;
an address latch enable line;
a command latch enable line;
a chip enable line;
an I/O for command, address and data; and
a ready/busy line.