Double data rate output latch for static RAM device has edge-triggered flip-flop to output DDR signal to synchronize with a second clock signal
View Patent ↗A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.
1. A Double Data Rate (DDR) output latch comprising:
a first edge triggered flip-flop for:
receiving a first clock signal;
receiving signals of a first part of a data bus; and
providing the signals of the first part of the data bus synchronized to the first clock signal,
a multiplexer for:
receiving the synchronized signals of the first part of the data bus and signals of a second part of the data bus; and
providing an output signal including either the synchronized signals of the first part of the data bus or the signals of the second part of the data bus depending on a multiplexor control signal,
an edge detector for providing a second clock signal having a rate substantially double a rate of the first clock signal,
a set-reset flip-flop for providing an output signal which changes state on both a rising and falling edge of the second clock signal,
a delay element for:
receiving the output signal from the set-reset flip-flop; and
providing the multiplexor control signal, and
a second edge triggered flip-flop for:
receiving the output signal from the multiplexor;
receiving the second clock signal; and
providing a DDR output signal synchronized to the second clock signal.
2. The DDR output latch as claimed in claim 1 wherein the first clock signal comprises a clock pair.
3. The DDR output latch as claimed in claim 1 wherein a width of the first part of the data bus and a width of the second part of the data bus are substantially equal to half of a width of the data bus.
4. The DDR output latch as claimed in claim 1 wherein:
signals of the data bus are provided by a transparent latch synchronized to a third clock signal; and
the third clock signal is a delayed version of the first clock signal.
5. The DDR output latch as claimed in claim 4 further comprising:
a delay locked loop (DLL) for receiving the third clock signal; and
providing the first clock signal.
6. A method for providing a Double Data Rate (DDR) output signal comprising:
receiving a first clock signal;
receiving signals of a first part of a data bus;
synchronizing the signals of the first part of the data bus to the first clock signal;
selecting either the signals of the first part of the data bus or the signals of the second part of the data bus depending on a multiplexor control signal;
providing a second clock signal having a rate substantially double a rate of the first clock signal;
providing the multiplexor control signal which changes state a predetermined delay after both a rising and falling edge of the second clock signal; and
synchronizing the selected one of the signals of the first part of the data bus or the signals of the second part of the data bus to the second clock signal and thereby providing a DDR output signal synchronized to the second clock signal.