Granted Patent B2

US 7,984,337 · App. 12/389,153 · Granted Jul 19, 2011

Abstract

Claims (51)

1. A data processing system that generates debug messages, comprising:

a data processor for executing a plurality of data processing instructions;

a memory coupled to the data processor for storing and providing information to the data processor;

debug circuitry coupled to the data processor for generating debug messages including address translation trace messages;

a memory management unit coupled to the debug circuitry and data processor, the memory management unit comprising address translation logic which stores address translation mappings and implements address translation using the address translation mappings to translate addresses between virtual and physical forms, wherein:

the debug circuitry comprises:

message generation circuitry coupled to the memory management unit for receiving notice when one or more of the address translation mappings are modified, the message generation circuitry generating an address translation trace message in response to detection of the modification of the one or more address translation mappings and providing the address translation trace message external to the debug circuitry.

2. The data processing system of claim 1 wherein the memory management unit sends an indicator signal to the message generation circuitry each time any address translation mapping is updated.

3. The data processing system of claim 2 wherein the message generation circuitry further comprises:

compression logic for selectively removing at least one field of the address translation trace message.

4. The data processing system of claim 3 wherein each of the at least one field of the address translation trace message that is removed by the compression logic contains a predetermined prevalent value for that field.

5. The data processing system of claim 4 wherein the predetermined prevalent value is controlled by a user of the data processing system, the predetermined prevalent value being stored in a storage location accessible by the user of the data processing system.

6. The data processing system of claim 3 wherein the at least one field that is removed is either an address translation size field or an address translation identification field for identifying one of a process identifier or an address space.

7. The data processing system of claim 1 wherein the one or more address translation mappings are stored in a translation lookaside buffer (TLB).

8. The data processing system of claim 7 wherein the memory management unit sends an indicator signal to the message generation circuitry each time the TLB writes a TLB entry or invalidates an entry.

9. The data processing system of claim 1 further comprising:

a debug terminal coupled to the debug circuitry; and

a debugger coupled to the debug terminal for receiving the address translation trace message from the debug circuitry.

10. A method for generating debug messages comprising:

executing a plurality of data processing instructions with a data processor;

coupling debug circuitry to the data processor for generating debug messages including address translation trace messages;

coupling a memory management unit to the debug circuitry and data processor, the memory management unit comprising a translation lookaside buffer (TLB) for implementing address translation to translate addresses between virtual and physical forms;

detecting when TLB entries are modified;

generating an address translation trace message in response to a detection of modification of a TLB entry; and

providing the address translation trace message to a debug terminal.

11. The method of claim 10 further comprising:

sending an indicator signal from the memory management unit to the message generation circuitry each time the TLB writes a TLB entry or invalidates an entry.

12. The method of claim 11 further comprising:

compressing a length of the address translation trace message by removing at least one field of the address translation trace message.

13. The method of claim 12 further comprising:

correlating the at least one field that is removed to an address translation size field or an address translation identification field for identifying an address space or a process identifier.

14. The method of claim 12 further comprising:

correlating a predetermined prevalent value to each of the at least one field of the address translation trace message; and

removing the at least one field only if the predetermined prevalent value exists for the at least one field.

15. The method of claim 14 further comprising:

controlling the predetermined prevalent value by a user of the data processing system; and

storing the predetermined value in one or more of a plurality of user accessible registers.

16. A data processing system, comprising:

global control circuitry for controlling the data processing system;

a data processor coupled to the global control circuitry, the data processor comprising an instruction fetch unit coupled to an instruction decoder, the instruction decoder coupled to one or more execution units for executing a plurality of data processing instructions;

a memory management unit coupled to the global control circuitry and the data processor, the memory management unit comprising address translation logic which stores address translation mappings and implements address translation using the address translation mappings to translate addresses between virtual and physical forms;

a bus interface unit for interfacing the memory management unit and a global interconnect;

a memory coupled to the global interconnect for storing and providing information from and to the data processor; and

debug circuitry coupled to the global control circuitry and the memory management unit, the debug circuitry generating debug messages including address translation trace messages, wherein:

the debug circuitry comprises:

message generation circuitry coupled to the memory management unit for receiving notice when one or more of the address translation mappings are modified, the message generation circuitry generating an address translation trace message in response to the detection of the modification of the one or more address translation mappings and providing the address translation trace message external to the debug circuitry.

17. The data processing system of claim 16 wherein the message generation circuitry further comprises:

compression logic for selectively removing at least one field of the address translation trace message.

18. The data processing system of claim 17 wherein each of the at least one field of the address translation trace message that is removed by the compression logic contains a predetermined prevalent value for that field.

19. The data processing system of claim 18 wherein the predetermined prevalent value is controlled by a user of the data processing system, the predetermined prevalent value being stored in a storage location accessible by the user of the data processing system.

20. The data processing system of claim 16 wherein the one or more address translation mappings are stored in a translation lookaside buffer (TLB) and the memory management unit sends an indicator signal to the message generation circuitry each time the TLB writes a TLB entry or invalidates an entry.

Assignments (13)