Stacked semiconductor devices including a master device
View Patent ↗A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s).
1. A system comprising:
a stack including:
a master chip that includes a plurality of memory cells; and
at least three slave memory chips, the three slave memory chips each lacking in at least some non-core circuitries to facilitate chip size reduction; and
a plurality of Through-Silicon Vias extending between the master chip and the three slave memory chips, the Through-Silicon Vias facilitating the master chip in providing the three slave memory chips with signals and operational voltages needed for respective device operations.
2. The system as claimed in claim 1 wherein the three slave memory chips are non-volatile memory chips.
3. The system as claimed in claim 2 wherein the master chip is a non-volatile memory chip.
4. The system as claimed in claim 1 wherein the master chip is a non-volatile memory chip.
5. The system as claimed in 1 further comprising a package printed circuit board, and the stack being connected to the package printed circuit board.
6. The system as claimed in 5 wherein the stack is connected to the package printed circuit board by flip chip and bumping.
7. The system as claimed in 5 further comprising wires connecting the package printed circuit board to the master chip.
8. The system as claimed in claim 1 wherein the master chip includes at least one chip area for one or more high voltage generators.
9. The system as claimed in claim 8 wherein each of the three slave memory chips have no chip areas for high voltage generators.
10. The system as claimed in claim 8 wherein the one or more high voltage generators comprise charge pumps.
11. The system as claimed in claim 1 wherein the master chip includes at least two chip areas for high voltage generators.
12. The system as claimed in claim 11 wherein each of the three slave memory chips have no chip areas for high voltage generators.
13. The system as claimed in claim 11 wherein the high voltage generators comprise charge pumps.
14. The system as claimed in claim 1 wherein the master chip is substantially larger dimensioned than any of the three slave memory chips.
15. The system as claimed in claim 1 wherein at least one of the three slave memory chips includes slave device test logic that is configured to be driven by the master chip during testing.
16. The system as claimed in claim 1 wherein each of the three slave memory chips includes core chip areas that take up more than eighty percent of total chip area.
17. The system as claimed in claim 1 wherein each of the three slave memory chips includes core chip areas that take up more than ninety percent of total chip area.
18. The system as claimed in 1 wherein the plurality of Through-Silicon Vias total at least more than one thousand in number.
19. The system as claimed in 1 wherein the plurality of Through-Silicon Vias total at least several thousand in number.
20. The system as claimed in 1 wherein the master chip further includes an address decoder, a pre-row decoder and a pre-column decoder for addressing the at least three slave memory chips.