Synchronous memory read data capture
View Patent ↗A method of snap-shot data training to determine the optimum timing of the DQS enable signal in a single read operation is provided. This is accomplished by first writing a Gray code count sequence into the memory and then reading it back in a single burst. The controller samples the read burst at a fixed interval from the time the command was issued to determine the loop-around delay. A simple truth table lookup determines the optimum DQS enable timing for normal reads. Advantageously, during normal read operations, the first positive edge of the enabled DQS signal is used to sample a counter that is enabled every time a command is issued. If the counter sample changes, indicating timing drift has occurred, the DQS enable signal can be adjusted to compensate for the drift and maintain a position centered in the DQS preamble. This technique can also be applied to a system that uses the iterative approach to determining DQS enable timing on power up. Another embodiment of the invention is a simple, low latency clock domain crossing circuit based on the DQS latched sample of the counter.
1. A method for enabling a data strobe input in a synchronous memory controller comprising:
determining a data strobe enable value and a data strobe edge value;
starting a counter upon issuance of a read command;
enabling the data strobe input when an output of the counter reaches the data strobe enable value;
latching the output of the counter with an edge of the data strobe input to provide a data strobe edge sample; and
if the data strobe edge sample differs from the data strobe edge value:
adding the difference between the data strobe edge sample and the data strobe edge value to the data strobe enable value, and
replacing the data strobe edge value with the data strobe edge sample.
2. The method as claimed in claim 1 wherein latching the output of the counter comprises latching the output of the counter on the first edge of the data strobe input following enabling the data strobe input.
3. The method as claimed in claim 1 wherein latching the output of the counter comprises latching the output of the counter on a rising edge of the data strobe input.
4. The method as claimed in claim 1 further comprising clocking the counter at four times a frequency of the data strobe input.
5. A method for enabling a data strobe input in a synchronous memory controller comprising:
determining a data strobe enable value, a first data strobe edge value, and a second data strobe edge value;
enabling the data strobe input following issuance of a read command at a time determined by the data strobe enable value;
latching a clock with an edge of the data strobe input for providing a first data strobe edge sample;
latching a phase shifted version of the clock with the edge of the data strobe input for providing a second data strobe edge sample; and
if the first data strobe edge sample differs from the first data strobe edge value or the second data strobe edge sample differs from the second data strobe edge value:
adjusting the data strobe enable value for compensating for drift, and
replacing the first data strobe edge value with the first data strobe edge sample and the second data strobe edge value with the second data strobe edge sample.
6. The method as claimed in claim 5 wherein the clock and the phase shifted version of the clock are latched on a first edge of the data strobe input following enabling the data strobe input.
7. The method as claimed in claim 5 wherein the clock and the phase shifted version of the clock are latched on a rising edge of the data strobe input.
8. The method as claimed in claim 5 wherein a frequency of the phase shifted version of the clock is substantially equal to a frequency of the clock.
9. The method as claimed in claim 8 wherein the phase shifted version of the clock is shifted 90 degrees with respect to the clock.
10. The method as claimed in claim 8 wherein the frequency of the phase shifted version of the clock and the frequency of the clock are substantially equal to a frequency of the data strobe input.
11. A method for enabling a data strobe input in a synchronous memory controller comprising:
determining a data strobe enable value and a data strobe edge value;
starting a counter upon issuance of a read command;
enabling the data strobe input when an output of the counter reaches the data strobe enable value;
latching the output of the counter with an edge of the data strobe input to provide a data strobe edge sample; and
adjusting the data strobe enable value based on the data strobe edge sample.
12. The method as claimed in claim 11, further comprising adjusting the data strobe edge value based on the data strobe edge sample.
13. The method as claimed in claim 12, wherein adjusting the data strobe edge value comprises replacing the data strobe edge value with the data strobe edge sample.
14. The method as claimed in claim 11 wherein latching the output of the counter comprises latching the output of the counter on the first edge of the data strobe input following enabling the data strobe input.
15. The method as claimed in claim 11 wherein latching the output of the counter comprises latching the output of the counter on a rising edge of the data strobe input.
16. The method as claimed in claim 11 further comprising clocking the counter at four times a frequency of the data strobe input.