Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage
View Patent ↗A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.
1. A method for erasing selected memory cells in a flash memory device, each memory cell consisting of a single non-volatile transistor, the method comprising:
biasing a p-well coupled to a plurality of memory cells, to a positive well bias voltage;
biasing a selected main word line coupled to a first terminal of a first NMOS transistor to a negative word line voltage;
biasing a plurality of unselected main word lines coupled to first terminals of a plurality of second NMOS transistors to a positive word line voltage;
selecting a plurality of local word line drivers coupled to respective main word lines, each main word line coupled to a plurality of local word lines;
driving a selected local word line to the negative word line voltage, the selected local word line being coupled to a second terminal of the first NMOS transistor, a first terminal of a third NMOS transistor and gate terminals of selected ones of the plurality of memory cells; and
driving a plurality of unselected local word lines to the positive word line voltage, the unselected local word lines being coupled to second terminals of the second NMOS transistors, first terminals of a plurality of fourth NMOS transistors and gate terminals of unselected ones of the plurality of memory cells,
wherein the difference between the positive well bias voltage and the negative word line voltage is sufficient to erase the selected memory cells.
2. The method as claimed in claim 1 wherein the difference between the positive well bias voltage and the positive word line voltage is insufficient to erase unselected memory cells.
3. The method as claimed in claim 1 wherein the positive well bias voltage is higher than V CC .
4. The method as claimed in claim 3 wherein the positive well bias voltage is approximately 7.5 volts.
5. The method as claimed in claim 1 wherein the positive well bias voltage is generated by a pump circuit.
6. The method as claimed in claim 1 wherein the negative word line voltage is higher in magnitude than V CC .
7. The method as claimed in claim 6 wherein the negative word line voltage is approximately −7.5 volts.
8. The method as claimed in claim 1 wherein the negative word line voltage is generated by a pump circuit.
9. The method as claimed in claim 1 wherein the positive word line voltage is less than V CC .
10. The method as claimed in claim 9 wherein the positive word line voltage is approximately 2.5 volts.
11. The method as claimed in claim 1 wherein the positive gate bias voltage is approximately 5 volts.
12. The method as claimed in claim 1 wherein each of the plurality of memory cells is coupled to one of a plurality of bit lines, and each of the plurality of bit lines is floating.
13. The method as claimed in claim 12 wherein each of the plurality of memory cells is directly connected to one of the plurality of bit lines.
14. The method as claimed in claim 1 wherein the plurality of memory cells are NOR-type-flash memory cells.
15. The method as claimed in claim 1 wherein the plurality of memory cells are organized in a parallel flash array.
16. The method as claimed in claim 1 wherein the plurality of memory cells are organized in a serial flash array.
17. The method as claimed in claim 1 wherein the single non-volatile transistor is a floating-gate transistor.
18. The method as claimed in claim 1 , further comprising biasing a second terminal of the third NMOS transistor to a negative voltage.
19. The method as claimed in claim 1 , further comprising biasing a substrate terminal of the first NMOS transistor and a substrate terminal of the third NMOS transistor a negative voltage.
20. The method as claimed in claim 1 , further comprising biasing second terminals of the plurality of fourth NMOS transistors to a ground voltage.