Method and system for creating secure address space using hardware memory router
View Patent ↗A method and system providing dynamic allocation of memory through hardware is disclosed. An embodiment provides for a multi-processor system providing for a secure partitioned memory. The system comprises a processor(s), a hardware implemented memory router coupled to the processor(s), and memory coupled to the memory router. The memory router stores memory partition information, which describes the memory allocated to the processor(s). Furthermore, the memory router maps a memory access request from a processor to an address in the memory.
1. A system having a partitioned memory, said system comprising:
a plurality of processors;
a hardware implemented memory router coupled to said processors; and
memory coupled to said memory router;
wherein said memory router is configured to store memory partition information describing the memory allocated to each of said plurality of processors; and
wherein said memory router is further operable to map memory access requests from said plurality of processors to respective addresses in said memory allocated to each of said plurality of processors.
2. The system of claim 1 , wherein:
said memory partition information further describes the type of access each processor of said plurality has to each portion of its allocated memory; and
said memory router is further operable to determine whether a memory access request having a first address from a first processor of said plurality is valid for said first address, based on the type of access and said first address.
3. The system of claim 2 , wherein said type of access is selected from the group consisting of read only, write only, and read/write access.
4. The system of claim 1 , wherein said router is re-configurable by altering said memory partition information, wherein said memory allocated to said plurality of processors is re-allocable.
5. The system of claim 1 , wherein said router is re-configurable by altering said memory partition information, wherein said type of access allocated to at least one processor of said plurality of processors is modifiable.
6. The system of claim 1 , wherein said memory router comprises a first component and a second component, said first and said second components coupled by a communication link;
said first component operable to add a key to said memory access request, said key identifying said second processor; and
said second component operable to use said key to route said request to said address in said memory allocated to said second processor, wherein multiple processors using the same communication link and using overlapping addresses securely access said memory.
7. The system of claim 1 , wherein said memory partition information is stored in a table containing a translation from processor address space to memory.
8. The system of claim 7 , wherein said table further comprises information allocating to a first processor of said plurality read only access to a first memory partition and to a second processor read and write access to said first memory partition.
9. The system of claim 1 , wherein more than one processor has access to a memory partition, wherein said memory is shared and said memory router has control over memory access.
10. The system of claim 1 , wherein said plurality of processors are coupled to said memory router via a single communication link.
11. The system of claim 1 , wherein said plurality of processors are coupled to said memory router via a plurality of communication links.
12. The system of claim 1 , wherein a first processor of said plurality runs a first operating system and said second processor of said plurality runs a second operating system and wherein said second processor is allowed to read the memory allocated to said first processor but is not allowed to write to said memory allocated to said first processor.
13. A method of partitioning memory, said method comprising the steps of:
a hardware implemented memory router receiving a request for memory access from one of a plurality of processors, said request specifying a first address;
said hardware memory router determining the location in memory corresponding to said first address, said memory partitioned among said plurality of processors;
said hardware memory router routing said memory request to said memory, wherein said memory access is securely executed such that said one of said plurality of processors is only able to access memory which is allocated to it; and
re-partitioning said memory by re-configuring said hardware memory router with commands entered via an external port to said memory router, wherein software executing on said plurality of processors is unable to modify said memory router.
14. A method of partitioning memory as recited in claim 13 further comprising:
changing the type of access that said one processor of said plurality has to a portion of said memory by re-configuring said memory router.
15. A method of partitioning memory as recited in claim 14 wherein said type of access is selected from the group consisting of read only, write only, and read/write access.
16. A method of partitioning memory as recited in claim 14 wherein said re-partitioning further comprises:
periodically re-configuring said memory router.
17. A method or partitioning memory as recited in claim 13 further comprising the steps of:
adding information to said memory request, said information specifying the processor or said plurality of processors which made said memory request, said plurality or processors sharing a communication link; and
after receiving said memory request via said communication link, said memory router using said information to determine which processor made said memory request.
18. A hardware implemented memory router comprising:
an input to receive a memory access request, said request specifying an address in a first processor's of a plurality of processors address space;
a table for storing memory partition information, said information describing the memory allocated to each of said plurality of processors;
logic operable to translate said address in said processor address space to a corresponding address in said memory; and
a first component and a second component, said first and said second components coupled by a communication link, wherein said first component is operable to add a key to said address specified by said processor request, said key identifying the processor of said plurality making said request; and wherein said second component is operable to use said key to route said request to the appropriate memory address, wherein multiple processors using the same communication link and using overlapping processor addresses securely access said memory.
19. The hardware implemented memory router of claim 18 , wherein:
said memory partition Information further describes the type of access each processor of said plurality has to each portion of its allocated memory; and
said memory router is further operable to determine whether said memory request from said first processor is valid for said address specified in said request, based on the type of access and said address specified in said request.
20. The memory router of claim 18 , further comprising an external port to said memory router, wherein commands entered via said external port are operable to re-configure said memory router to re-partition memory allocation to said plurality of processors.