Memory device with manufacturable cylindrical storage node
View Patent ↗A high capacitance embedded capacitor and associated fabrication processes are disclosed for fabricating a capacitor stack in a multi-layer stack to include a first capacitor plate conductor formed with a cylinder-shaped storage node electrode formed in the multi-layer stack, a capacitor dielectric layer surrounding the cylinder-shaped storage node electrode, and a second capacitor plate conductor formed from a conductive layer in the multi-layer stack that is sandwiched between a bottom and top dielectric layer, where the cylinder-shaped storage node electrode is surrounded by and extends through the conductive layer.
1. A method for manufacturing a semiconductor device, comprising:
forming a conductive pad;
forming a first insulating layer directly on the conductive pad;
forming a second insulating layer over the first insulating layer;
forming a first hole within the first and the second insulating layer such that an upper surface portion of the conductive pad is exposed;
forming a conformal dielectric layer within the first hole and directly on an exposed portion of the conductive pad, the conformal dielectric layer partially filling the first hole;
forming a conformal first conductive layer within the first hole and over the conformal dielectric layer, the first conductive layer partially filling the first hole;
etching the first conductive layer and the conformal dielectric layer using an anisotropic etch process such that a sidewall portion of the first conductive layer along the height of the first hole and a sidewall portion of the conformal dielectric layer along the height of the first hole remain unremoved and at least a bottom portion of the first conductive layer and a bottom portion of the conformal dielectric layer within the first hole are removed to expose a portion of the conductive pad;
forming a second conductive layer within the first hole and on the first conductive layer such that the second conductive layer is in direct contact with the first conductive layer and the conductive pad;
forming a third insulating layer over the second insulating layer;
forming a second hole in the third insulating layer such that at least one of the first and the second conductive layers is exposed; and
forming a third conductive layer within the second hole, the third conductive layer being in direct contact with the exposed at least one of the first and the second conductive layers.
2. The method of claim 1 , wherein the first conductive layer comprises polysilicon.
3. The method of claim 2 , wherein the second conductive layer comprises polysilicon.
4. The method of claim 1 , wherein the conductive pad is wider than the first hole.
5. The method of claim 1 , wherein forming the conductive pad, comprises:
forming a premetal dielectric layer on a semiconductor substrate;
forming a contact within the premetal dielectric layer; and
forming the conductive pad on the contact.
6. The method of claim 5 , prior to forming the premetal dielectric layer, further comprising:
forming a gate on the semiconductor substrate; and
forming the contact adjacent the gate, wherein the gate is a select transistor for a memory device.
7. The method of claim 1 , further comprising forming a fourth conductive layer between the first and the second insulating layer.
8. The method of claim 7 , wherein the fourth conductive layer comprises at least one of Ta, TaN, TiN and WN.
9. The method of claim 1 , wherein the conformal dielectric layer comprises silicon nitride.
10. The method of claim 6 , wherein the memory device is a DRAM device.