Semiconductor device for reducing parasitic capacitance produced in the vicinity of a transistor located within the semiconductor device
View Patent ↗A semiconductor device includes: a gate electrode formed on a substrate; impurity regions formed in the substrate and to both sides of the gate electrode; a first interlayer insulating film formed to cover the gate electrode; and a second interlayer insulating film formed so as to be aligned in a direction parallel to the principal surface of the substrate and adjacent to the gate electrode with a part of the first interlayer insulating film interposed therebetween. The second interlayer insulating film has a lower relative permeability than the first interlayer insulating film.
1. A semiconductor device comprising:
a gate electrode formed on a substrate;
impurity regions formed in the substrate and to both sides of the gate electrode;
a first interlayer insulating film formed to cover the gate electrode; and
a second interlayer insulating film formed so as to be aligned in a direction parallel to the principal surface of the substrate and adjacent to the gate electrode with a part of the first interlayer insulating film interposed therebetween,
wherein the second interlayer insulating film has a lower relative permeability than the first interlayer insulating film.
2. The semiconductor device of claim 1 further comprising:
LDD (Lightly Doped Drain) regions formed in regions of the substrate located to both sides of the gate electrode;
sidewalls formed on both sides of the gate electrode; and
a liner film formed to cover the substrate, the gate electrode and the sidewalls.
3. The semiconductor device of claim 1 , wherein
the second interlayer insulating film is formed on the impurity region.
4. The semiconductor device of claim 1 , wherein
contact plugs are formed in the first interlayer insulating film to reach the impurity regions.
5. The semiconductor device of claim 1 , wherein
contact plugs are formed in the second interlayer insulating film to reach the impurity regions.
6. The semiconductor device of claim 1 , wherein
contact plugs are formed across the border between the first interlayer insulating film and the second interlayer insulating film to reach the impurity regions.
7. The semiconductor device of claim 1 further comprising
an isolation region formed in the substrate to surround the impurity regions.
8. The semiconductor device of claim 7 , wherein
the second interlayer insulating film is formed on the isolation region.
9. The semiconductor device of claim 7 , wherein
the second interlayer insulating film is formed across the border between the impurity region and the isolation region.
10. A semiconductor device comprising:
a gate electrode formed on a substrate;
impurity regions formed in the substrate and to both sides of the gate electrode;
an interlayer insulating film formed to cover the gate electrode;
a hollow region formed so as to be aligned in a direction parallel to the principal surface of the substrate and adjacent to the gate electrode with a part of the interlayer insulating film interposed therebetween; and
an isolation region formed in the substrate to surround the impurity regions,
wherein the hollow region is formed on the isolation region.
11. The semiconductor device of claim 10 , wherein
contact plugs are formed in the interlayer insulating film to reach the impurity regions.
12. A semiconductor device comprising:
a gate electrode formed on a substrate;
impurity regions formed in the substrate and to both sides of the gate electrode;
an interlayer insulating film formed to cover the gate electrode;
a hollow region formed so as to be aligned in a direction parallel to the principal surface of the substrate and adjacent to the gate electrode with a part of the interlayer insulating film interposed therebetween; and
an isolation region formed in the substrate to surround the impurity regions,
wherein the hollow region is formed across the border between the impurity region and the isolation region.
13. The semiconductor device of claim 12 , wherein
contact plugs are formed in the interlayer insulating film to reach the impurity regions.
14. A semiconductor
device comprising:
a gate electrode formed on a substrate;
impurity regions formed in the substrate and to both sides of the gate electrode;
an interlayer insulating film formed to cover the gate electrode; and
a hollow region formed so as to be aligned in a direction parallel to the principal surface of the substrate and adjacent to the gate electrode with a part of the interlayer insulating film interposed therebetween,
wherein the hollow region is formed on the impurity region, and
wherein contact plugs are formed in the interlayer insulating film to reach the impurity regions.
15. A semiconductor device comprising:
a gate electrode formed on a substrate;
impurity regions formed in the substrate and to both sides of the gate electrode;
an interlayer insulating film formed to cover the gate electrode; and
a hollow region formed so as to be aligned in a direction parallel to the principal surface of the substrate and adjacent to the gate electrode with a part of the interlayer insulating film interposed therebetween,
wherein a contact plug is formed in the hollow region and a part of the interlayer insulating film located on the hollow region to reach the impurity region.
16. A semiconductor device comprising:
a gate electrode formed on a substrate;
impurity regions formed in the substrate and to both sides of the gate electrode;
an interlayer insulating film formed to cover the gate electrode; and
a hollow region formed so as to be aligned in a direction parallel to the principal surface of the substrate and adjacent to the gate electrode with a part of the interlayer insulating film interposed therebetween,
wherein a contact plug is formed across the border between a combination of the hollow region and a part of the interlayer insulating film located on the hollow region and the interlayer insulating film to reach the impurity region.