Clock mode determination in a memory system
View Patent ↗A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.
1. A system comprising:
a memory controller; and
at least one memory device communicatively coupled to the memory controller, the memory device including:
a mode selection circuit configured to provide a mode selection signal;
first and second input terminals; and
circuitry configured to compare, when the mode selection signal is at a first logic level, two signals receivable by the first and second input terminals in providing a buffered signal, and
the memory device being configured for: i) operation at a first speed when the mode selection signal is at the first logic level; and ii) operation at a second speed when the mode selection signal is at a second logic level, the second speed being less than the first speed.
2. The system of claim 1 , wherein:
the first input terminal is a reference voltage input terminal configured to receive an input reference voltage signal;
the second input terminal is a data input terminal configured to receive a write data input signal;
the circuitry comprises a data input buffer;
the two signals receivable by the first and second input terminals are the input reference voltage signal and the write data input signal;
the buffered signal is a buffered data input signal; and
when the mode selection signal is at the second logic level, the data input buffer is configured to provide the buffered data input signal independent of the input reference voltage signal.
3. The system of claim 2 , wherein:
the data input buffer further includes a buffer circuit having a single input coupled to the data input terminal; and
a comparator circuit portion of the circuitry is disabled when the mode selection signal is at the second logic level, and the buffer circuit is disabled when the mode selection signal is at the first logic level.
4. The system of claim 2 , wherein the data input buffer further includes:
a buffer circuit having a single input coupled to the data input terminal; and
a multiplexer circuit coupled to the output of a comparator circuit portion of the circuitry and the output the buffer circuit, the multiplexer circuit being configured to provide a signal from the comparator circuit as the buffered data input signal when the mode selection signal is at the first logic level, and the multiplexer circuit being further configured to provide a signal from the buffer circuit as the buffered data input signal when the mode selection signal is at the second logic level.
5. The system of claim 2 , wherein the mode selection circuit is configured to determine a state of the mode selection signal based on the input reference voltage signal.
6. The system of claim 2 , wherein the write data input signal is a double data rate signal.
7. The system of claim 1 , wherein:
the first input terminal is a positive clock input terminal to receive a positive clock input signal;
the second input terminal is a negative clock input terminal to receive a negative clock input signal;
the two signals are the positive clock input signal and the negative clock input signal;
the buffered signal is a buffered clock input signal; and
when the mode selection signal is at the second logic level, the circuitry is configured to provide the buffered clock input signal based on either the positive clock input signal or the negative clock input signal.
8. The system of claim 7 , wherein:
the circuitry further includes a first buffer circuit having a single input coupled to either the positive clock input terminal or the negative clock input terminal; and
a comparator circuit portion of the circuitry is disabled when the mode selection signal is at the second logic level, and the first buffer circuit is disabled when the mode selection signal is at the first logic level.
9. The system of claim 7 , wherein the circuitry further includes:
a first buffer circuit having a single input coupled to either the positive clock input terminal or the negative clock input terminal; and
a multiplexer circuit in communication with the output of a comparator circuit portion of the circuitry and coupled to the output of the first buffer circuit.
10. The system of claim 7 , wherein the circuitry further includes:
a first buffer circuit having a single input coupled to the positive clock input terminal; and
a second buffer circuit having a single input coupled to the negative clock input terminal.
11. The system of claim 7 , wherein the circuitry includes a delay locked loop coupled to the circuitry to provide a phase shifted buffered clock input signal in connection with operation at the first speed.
12. The system of claim 1 , wherein at least one of the two signals is an SSTL signal or an HSTL signal when operating at the first speed.
13. The system of claim 1 , wherein at least one of the two signals is an LVTTL signal or an un-terminated low voltage CMOS signal when operating at the second speed.
14. The system of claim 1 , wherein the at least one memory device is an at least one serially connected memory device.
15. A memory device, comprising:
a mode selection circuit configured to provide a mode selection signal;
a first input terminal configured to receive a first signal;
a second input terminal configured to receive a second signal;
circuitry configurable to generate internal signals based on the first signal and the second signal, the internal signals causing operation at a first speed when the mode selection signal is at a first logic level, and at a second speed when the mode selection signal is at a second logic level, the first speed being greater than the second speed.
16. The memory device of claim 15 , wherein the first signal is a reference voltage and the second signal includes data.
17. The memory device of claim 16 , wherein the circuitry includes
a data buffer configurable by the mode selection signal at the first logic level to compare the data to the reference voltage to provide an internal data signal, and configurable by the mode selection signal at the second logic level to buffer the data as the internal data signal.
18. The memory device of claim 17 , wherein the circuitry further includes
data circuitry including latches operating at the first speed or the second speed for latching the internal data signal.
19. The memory device of claim 15 , wherein the first signal is a positive clock signal and the second signal is a negative clock signal.
20. The memory device of claim 19 , wherein the circuitry includes
a clock buffer configurable by the mode selection signal at the first logic level to compare the positive clock signal to the negative clock signal for providing an internal clock signal, and configurable by the mode selection signal at the second logic level to buffer the positive clock signal and the negative clock signal.
21. The memory device of claim 20 , wherein the circuitry further includes
clock circuitry configurable by the mode selection signal at the first logic level to generate phase shifted clock signals relative to the internal clock signal as internal positive and negative clock signals, and configurable by the mode selection signal at the second logic level to provide the positive clock signal and the negative clock signal as the internal positive and negative clock signals.
22. The memory device of claim 21 , wherein the clock circuitry includes a phase locked loop for generating the phase shifted internal clock signals in response to the internal clock signal.
23. The memory device of claim 21 , wherein the clock circuitry includes a delayed locked loop for generating the phase shifted internal clock signals in response to the internal clock signal.