Dynamic random access memory and boosted voltage producer therefor
View Patent ↗A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump circuits that are selectively activated by a pump control circuit based on a refresh time for refreshing data in the DRAM cells in the sleep mode.
1. A memory device comprising:
a plurality of storage cells for storing data;
a plurality of selectively activatable charge pumps for providing a boosted voltage for operation of the memory device; and
a controller for selectively activating the plurality of charge pumps,
the memory device being operable in a plurality of modes including an auto-refresh mode and a self-refresh mode, each mode being characterized by the activation of a different number of the plurality of charge pumps.
2. The memory device of claim 1 , wherein:
the memory device is a dynamic random access memory (DRAM) memory device; and
the plurality of storage cells are a plurality of DRAM storage cells.
3. The memory device of claim 2 , wherein:
the auto-refresh mode provides that the DRAM storage cells are refreshed at an active mode refresh rate; and
the self-refresh mode provides that the DRAM storage cells are refreshed at a reduced-power mode refresh rate slower than the active mode refresh rate.
4. The memory device of claim 3 , wherein:
the active mode refresh rate corresponds to a rate of an auto-refresh operation during the active mode; and
each reduced-power mode refresh rate corresponds to a rate of a self-refresh operation during the corresponding reduced-power mode.
5. The memory device of claim 4 , wherein the controller selects a mode of operation of the memory device based on a current refresh rate of the DRAM storage cells.
6. The memory device of claim 1 , wherein the controller selectively activates the plurality of charge pumps by outputting an enable signal to each of the plurality of charge pumps.
7. The memory device of claim 1 , wherein each of the plurality of modes corresponds to one of a plurality of refresh time periods.
8. The memory device of claim 1 , wherein each of the plurality of charge pumps provides an equal amount of voltage boost when activated.
9. A method of operating a memory device, comprising:
determining whether the memory is operating in an auto-refresh mode or a self-refresh mode;
if the memory is operating in a self-refresh mode:
selecting a number of segments of a pump circuit based on a required current of the memory device; and
activating the selected segments;
wherein the memory device is a dynamic random access memory (DRAM) device, and the method further includes
determining the required current of the memory device based on a refresh rate of the memory device.
10. A method of operating a memory device, comprising:
determining whether the memory is operating in an auto-refresh mode or a self-refresh mode;
if the memory is operating in a self-refresh mode:
selecting a number of segments of a pump circuit based on a required current of the memory device; and
activating the selected segments;
combining the outputs of the selected segments to produce an output voltage; and
deactivating the pump circuit when an operating voltage of the memory device is higher than a predetermined voltage level.