Synthesizer, synthesizer module, and reception device and electronic device using same

1. A synthesizer, comprising:

a comparator for receiving a reference oscillation signal from a reference oscillator;

an oscillator for outputting an oscillation signal based on a comparison signal from the comparator;

a frequency divider for dividing a frequency of the oscillation signal from the oscillator responsive to a controller, to form a frequency divided signal, the frequency divider including an accumulator for generating a cumulative addition value during a frequency division ratio based on a frequency division number from the controller; and

a frequency error detector for detecting an error between a preset frequency and the frequency based on the reference oscillation signal,

wherein the comparator compares the frequency divided signal from the frequency divider with the reference oscillation signal from the reference oscillator, and outputs the comparison signal showing a comparison result to the oscillator, and

the controller changes the frequency division ratio of the frequency divider from a first ratio to a second ratio via the accumulator based on the detected error from the frequency error detector, such that a last cumulative addition value of the first ratio is used as an initial addition value of the accumulator for the second ratio.

2. The synthesizer of claim 1 ,

wherein the frequency division number that changes the frequency division ratio of the frequency divider consists of an integer part and a fractional part, and the controller changes the frequency division ratio in a state in which the fractional part of the frequency division number is kept at a past value.

3. The synthesizer of claim 2 ,

wherein the controller changes a fractional frequency division number so that a difference between a frequency immediately before switching of the frequency division number of the frequency divider and a frequency after switching of the frequency division number of the frequency divider falls within a lock range.

4. The synthesizer of claim 1 ,

wherein the frequency division number that changes the frequency division ratio of the frequency divider consists of an integer part and a fractional part,

when the controller changes the frequency division ratio of the frequency divider based on the detected error from the frequency error detector,

in a case in which the controller does not change an integer frequency division number to be input into the integer part but changes only a fractional frequency division number to be input into the fractional part in the frequency division number of the frequency divider, the fractional frequency division number is input into the fractional part in a state in which the fractional part is kept at a past value and the integer frequency division number to be input into the integer part is changed to a larger value than a past value, and

in a case in which the controller arbitrarily changes also the fractional frequency division number to be input into the fractional part, the fractional frequency division number from the controller is input into the fractional part after the fractional part is returned to a minimum value.

5. The synthesizer of claim 1 ,

wherein the frequency division number that changes the frequency division ratio of the frequency divider consists of an integer part and a fractional part,

when the controller changes the frequency division ratio of the frequency divider based on the detected error from the frequency error detector,

in a case in which the controller does not change an integer frequency division number to be input into the integer part but changes only a fractional frequency division number to be input into the fractional part in the frequency division number of the frequency divider, the fractional frequency division number is input into the fractional part in a state in which the fractional part is kept at a past value and the integer frequency division number to be input into the integer part is changed to a smaller value than a past value, and

in a case in which the controller arbitrarily changes also the fractional frequency division number to be input into the fractional part, the fractional frequency division number from the controller is input into the fractional part after the fractional part is returned to a maximum value.

6. The synthesizer of claim 1 ,

wherein the reference oscillator includes a micro electro mechanical system element.

7. The synthesizer of claim 1 ,

wherein the frequency error detector detects the error between the preset frequency and the frequency based on the reference oscillation signal based on an output signal from a temperature sensor for detecting a temperature.

8. A synthesizer module comprising:

a synthesizer of claim 1 , and

a reference oscillator formed of a resonator including a micro electro mechanical system element,

wherein an output signal from the reference oscillator is input into the comparator.

9. The synthesizer module of claim 8 ,

wherein the synthesizer and the resonator including the micro electro mechanical system element are formed on a same semiconductor substrate.

10. A reception device comprising:

a synthesizer of claim 1 , and

a mixer for converting a frequency of a received signal based on the oscillation signal from the synthesizer.

11. The reception device of claim 10 ,

wherein a change in a frequency of the reference oscillation signal from the reference oscillator is based on an output signal from the synthesizer.

12. The reception device of claim 10 ,

wherein when the frequency of the received signal is switched, the controller changes the frequency division ratio of the frequency divider in a state in which the frequency division ratio is returned to a preset value.

13. The reception device of claim 10 ,

wherein the frequency division number that changes the frequency division ratio of the frequency divider consists of an integer part and a fractional part, and

when the frequency of the received signal is switched, the integer part is changed, and

when the frequency division ratio of the frequency divider is changed based on the detected error from the frequency error detector, the fractional part is changed.

14. The reception device of claim 10 ,

wherein during a term in which the controller determines that predetermined data are not received, the controller changes the frequency division ratio by returning it to a preset value, and during a term in which the controller determines that predetermined data are received, the controller changes the frequency division ratio without returning it to the preset value and in a state in which a past value is kept.

15. The reception device of claim 14 ,

wherein the term in which the controller determines that predetermined data are not received is a guard interval term.

16. An electronic device comprising:

a wireless device including a synthesizer of claim 1 and which transmits and receives a signal by using a plurality of frequency channels.

17. An electronic device comprising:

a synthesizer of claim 1 ;

a mixer for converting a frequency of a received signal based on the oscillation signal from the synthesizer;

a signal processing section connected to an output side of the mixer; and

a display section connected to an output side of the signal processing section.