Hierarchical common source line structure in NAND flash memory
View Patent ↗Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line may be called a Global Common Source Line (GCSL). In an array of NAND flash cell blocks, only one NAND flash cell block is selected at a time for programming. To reduce power consumption, only the selected NAND flash cell block receives a value on the CSL that is indicative of the value on the GCSL. Additionally, the CSLs of non-selected NAND flash cell blocks may be disabled through an active connection to ground.
1. A memory system including a NAND Flash memory device, the device comprising:
a cell block including:
a page buffer;
a first NAND flash memory string connected to a local common source line and connected, by a first bit line via a first bit select line transistor, to the page buffer;
a second NAND flash memory string connected to the local common source line and connected, by a second bit line via a second bit select line transistor, to the page buffer, and
a local switch logic including:
a first semiconductor switch for selectively allowing passage of a signal received on a global common source line to the cell block on the local common source line; and
a second semiconductor switch for selectively allowing passage of a predetermined voltage on the local common source line.
2. The memory system as claimed in claim 1 wherein the predetermined voltage is ground.
3. The memory system as claimed in claim 1 wherein the local switch logic further comprises a first input line for receiving a global common source line signal.
4. The memory system as claimed in claim 1 wherein the local switch logic further comprises a second input line for receiving a voltage level indicative of the cell block not having been selected.
5. The memory system as claimed in claim 1 wherein the local switch logic further comprises a third input line for receiving a ground select signal.
6. The memory system as claimed in claim 5 wherein the local switch logic further comprises a third semiconductor switch for selectively allowing a passage of the ground select signal to a ground select line in the cell block.
7. The memory system as claimed in claim 6 wherein the plurality of NAND flash memory strings is connected to the ground select line.
8. The memory system as claimed in claim 5 further comprising a row decoder adapted to receive row pre-decoded signals and based on the row pre-decoded signals, provide, on the third input line, the ground select signal.
9. The memory system as claimed in claim 1 wherein the local switch logic further comprises a fourth input line for receiving a block decode signal from a local charge pump.
10. The memory system as claimed in claim 9 wherein the local charge pump is adapted to receive a block decode latch signal and provide the block decode signal to the first and the third semiconductor switches.
11. The memory system as claimed in claim 10 wherein the passage of the ground select signal is based on the block decode signal on the fourth input line.
12. The memory system of claim 1 further comprising:
a first bit select line connected to a gate of the first bit select line transistor; and
a second bit select line connected to a gate of the second bit select line transistor.
13. The memory system of claim 1 wherein the first bit select line transistor is associated with an odd bit and said second bit select line transistor is associated with and even bit.
14. The memory system of claim 12 adapted, when a row address of a memory cell of interest is odd, to:
receive a high value at the gate of the first bit select line transistor; and
receive a low value at the gate of the second bit select line transistor.
15. The memory system of claim 12 adapted, when a row address of a memory cell of interest is even, to:
receive a low value at the gate of the first bit select line transistor; and
receive a high value at the gate of the second bit select line transistor.