Output buffer slew rate control using clock signal

1. A method comprising:

identifying delay of a generated signal through circuitry for an output buffer, wherein the delay is relative to a clock signal; and

independently controlling each of a falling edge slew rate and a rising edge slew rate of the circuitry in response to the identifying.

2. The method of claim 1 , wherein the identifying comprises identifying a delay for generating an edge cycle completion signal relative to an amount of time defined by a clock signal.

3. The method of claim 1 , wherein the identifying comprises detecting an edge of the generated signal relative to an edge of the clock signal.

4. The method of claim 1 , wherein the identifying comprises identifying a delay of the circuitry in generating a rising signal edge relative to an amount of time defined by the clock signal; and

wherein the method comprises identifying a delay of the circuitry for an output buffer in generating a falling signal edge relative to an amount of time defined by the clock signal.

5. The method of claim 1 , comprising independently controlling a falling edge slew rate and a rising edge slew rate of one or more output buffers in response to the identifying.

6. A method comprising:

detecting a rising edge generated by circuitry for an output buffer relative to a first edge of a clock signal;

detecting a falling edge generated by the circuitry relative to a second edge of the clock signal; and

independently controlling rising and falling edge slew rates of the circuitry in response to the detecting.

7. The method of claim 6 , comprising inputting another clock signal into the circuitry.

8. The method of claim 6 , wherein the detecting the rising signal edge comprises detecting a rising edge of an edge cycle completion signal generated by the circuitry; and

wherein the detecting the falling signal edge comprises detecting a falling edge of an edge cycle completion signal generated by the circuitry for an output buffer.

9. The method of claim 6 , comprising independently controlling rising and falling signal edge slew rates of one or more output buffers in response to the detecting.

10. An apparatus comprising:

circuitry for an output buffer;

an edge detector receiving a clock signal and a signal generated by the circuitry, wherein the edge detector identifies delays of the generated signal relative to an amount of time defined by the clock signal; and

a slew rate signal generator generating one or more slew rate control signals in response to the delays, wherein the slew rate control signals independently control each of a falling edge slew rate and a rising edge slew rate of the circuitry.

11. The apparatus of claim 10 , wherein the signal generated by the circuitry for an output buffer is an edge cycle completion signal.

12. The apparatus of claim 10 , wherein the edge detector identifies a delay of the circuitry in generating a rising edge relative to an amount of time defined by the clock signal, wherein the edge detector identifies a delay of the circuitry in generating a falling edge relative to an amount of time defined by the clock signal.

13. The apparatus of claim 10 , comprising one or more output buffers, wherein the slew rate control signal generator is to generate one or more slew rate control signals to control at least one of the falling edge slew rate and the rising edge slew rate of the one or more output buffers.

14. An apparatus comprising:

circuitry for an output buffer, the circuitry providing a generated signal;

a rising edge detector for detecting a rising edge of the generated signal relative to a first edge of a clock signal;

a falling edge detector for detecting a falling edge of the generated signal relative to a second edge of the clock signal; and

a slew rate control signal generator independently controlling a falling edge slew rate and a rising edge slew rate of the circuitry in response to the detected falling and rising edges.

15. The apparatus of claim 14 , comprising an input signal generator providing the clock signal as an input to the circuitry.

16. The apparatus of claim 14 , wherein the generated signal is an edge cycle completion signal.

17. The apparatus of claim 14 , comprising one or more output buffers, wherein the slew rate control signal generator generates slew rate control signals to control rising and falling edge slew rates independently for the one or more output buffers.

18. An apparatus comprising:

circuitry for an output buffer, the circuitry providing a generated signal;

means for identifying one or more delays of the generated signal relative to an amount of time defined by a clock signal; and

means for independently controlling a falling edge slew rate and a rising edge slew rate of the circuitry in response to the delays.

19. The apparatus of claim 18 , comprising one or more output buffers; and

means for independently controlling a falling edge slew rate and a rising edge slew rate of the one or more output buffers.

20. An apparatus comprising:

circuitry for an output buffer;

means for detecting rising and falling edges of a signal generated by the circuitry relative to edges of a clock signal; and

means for independently controlling rising and falling edge slew rates of the circuitry.

21. The apparatus of claim 20 , comprising one or more output buffers; and

means for independently controlling rising and falling edge slew rates of the one or more output buffers.

22. A system comprising:

a bus comprising one or more lines;

a clock source to generate a clock signal; and

a plurality of devices coupled to the bus, wherein at least one device is coupled to the clock source and comprises one or more output buffers to output signals over one or more lines of the bus and a slew rate controller to identify one or more delays of circuitry for an output buffer in generating a signal relative to an amount of time defined using the clock signal and to independently control each of a falling edge slew rate and a rising edge slew rate of the circuitry based on the identified delay.

23. The system of claim 22 , wherein the slew rate controller is to identify a delay of the circuitry in generating a rising edge of the signal relative to an amount of time defined using the clock signal and is to identify a delay of the circuitry in generating a falling edge of the signal relative to an amount of time defined using the clock signal.

24. A system comprising:

a bus comprising one or more lines;

a clock source to generate a clock signal; and

a plurality of devices coupled to the bus, wherein at least one device is coupled to the clock source and comprises one or more output buffers to output signals over one or more lines of the bus and a slew rate controller to detect rising and falling edges of a signal generated by circuitry for an output buffer relative to edges defined using the clock signal, wherein the slew rate controller independently controls rising and falling edge slew rates for both the circuitry and the one or more output buffers based on the detections.