Flash multi-level threshold distribution scheme
View Patent ↗A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while extending the life span of the multi-level Flash cells as the threshold voltage distance between programmed states is maximized. The erase voltage domain can be less than 0V while a program voltage domain is greater than 0V. Accordingly, circuits for program verifying and reading multi-level Flash cells having a programmed threshold voltage in the erase voltage domain and the program voltage domain use negative and positive high voltages.
1. A method for verifying a programmed state of a flash memory cell coupled to a bitline, comprising:
driving a wordline connected to the flash memory cell with a negative reference voltage;
determining failed programming of the flash memory cell to the programmed state if a voltage level of the bitline changes in response to the wordline at the negative reference voltage.
2. The method of claim 1 , further including precharging the bitline to the voltage level before driving the wordline.
3. The method of claim 1 , wherein determining includes sensing a change in the voltage level of the bitline when the flash memory cell turns on in response to the wordline at the negative reference voltage.
4. The method of claim 1 , wherein the programmed state corresponds to a first cell state, and the negative reference voltage is greater than a negative threshold voltage corresponding to a second cell state of the flash memory cell.
5. The method of claim 4 , wherein the second cell state corresponds to an erased state.
6. The method of claim 4 , wherein the second cell state corresponds to another programmed state.
7. The method of claim 1 , wherein the programmed state has a threshold voltage range defined by a lower voltage limit and an upper voltage limit greater than the lower voltage limit, the lower voltage limit being a negative voltage.
8. The method of claim 7 , wherein the upper voltage limit is another negative voltage.
9. The method of claim 7 , wherein the upper voltage limit is a positive voltage.
10. The method of claim 3 , wherein the programmed state corresponds to a first programmed state, and the flash memory cell is programmable to a second programmed state having a threshold voltage greater than the upper voltage limit.