Semiconductor integrated circuit and design method thereof
View Patent ↗In a layout process of a semiconductor integrated circuit, a power supply is initially formed in an arrangement in which the current threshold value is not exceeded. In a case where the excess over the current threshold value occurs after the power supply is formed, the power supply arrangement is changed according to the current threshold value, design rule data base, and power supply wiring density so as not to exceed the current threshold value.
1. A semiconductor integrated circuit comprising:
a first power supply source IO terminal;
a first power supply source wire; and
a first ring power supply, wherein:
the first power supply source IO terminal is connected to the first power supply source wire,
the first power supply source wire is connected to the first ring power supply,
the first power supply source wire includes a first branched wire, and
the first branched wire is connected to the first ring power supply.
2. The semiconductor integrated circuit of claim 1 , wherein
each of the first power supply source wire and the first branched wire includes a plurality of wire layers.
3. The semiconductor integrated circuit of claim 2 , further comprising:
a second ring power supply;
a third power supply source wire; and
a third power supply source IO terminal, wherein:
each of the first ring power supply and the second ring power supply includes a plurality of wire layers,
the first ring power supply is connected to the first power supply source wire in at least one of the plurality of wire layers,
the second ring power supply is connected to the third power supply source wire in at least one of the plurality of wire layers,
the third power supply source IO terminal is connected to the third power supply source wire,
the first power supply source IO terminal and the third power supply source IO terminal in a pair are disposed outside the first ring power supply and the second ring power supply in a pair when viewed in plan, and
the wire layers of the first power supply source wire and the third power supply source wire are the same wire layer.
4. The semiconductor integrated circuit of claim 1 , further comprising:
a second power supply source IO terminal; and
a second power supply source wire, wherein:
the second power supply source IO terminal is connected to the second power supply source wire, and
the second power supply source wire is connected to the first ring power supply and the first branched wire.
5. The semiconductor integrated circuit of claim 4 , wherein
the second power supply source wire includes a plurality of wire layers.
6. The semiconductor integrated circuit of claim 5 , further comprising:
a second ring power supply;
a third power supply source wire; and
a third power supply source IO terminal, wherein:
each of the first ring power supply and the second ring power supply includes a plurality of wire layers,
the first ring power supply is connected to the first power supply source wire in at least one of the plurality of wire layers,
the second ring power supply is connected to the third power supply source wire in at least one of the plurality of wire layers,
the third power supply source IO terminal is connected to the third power supply source wire,
the first power supply source IO terminal and the third power supply source IO terminal in a pair are disposed outside the first ring power supply and the second ring power supply in a pair when viewed in plan, and
the wire layers of the first power supply source wire and the third power supply source wire are the same wire layer.
7. The semiconductor integrated circuit of claim 4 , wherein:
the first power supply source wire further includes a second branched wire, and
the second power supply source wire is connected to the second branched wire.
8. The semiconductor integrated circuit of claim 7 , wherein
each of the second power supply source wire and the second branched wire includes a plurality of wire layers.
9. The semiconductor integrated circuit of claim 8 , further comprising:
a second ring power supply;
a third power supply source wire; and
a third power supply source IO terminal, wherein:
each of the first ring power supply and the second ring power supply includes a plurality of wire layers,
the first ring power supply is connected to the first power supply source wire in at least one of the plurality of wire layers,
the second ring power supply is connected to the third power supply source wire in at least one of the plurality of wire layers,
the third power supply source IO terminal is connected to the third power supply source wire,
the first power supply source IO terminal and the third power supply source IO terminal in a pair are disposed outside the first ring power supply and the second ring power supply in a pair when viewed in plan, and
the wire layers of the first power supply source wire and the third power supply source wire are the same wire layer.
10. The semiconductor integrated circuit of claim 4 , further comprising:
a second ring power supply;
a third power supply source wire; and
a third power supply source IO terminal, wherein:
each of the first ring power supply and the second ring power supply includes a plurality of wire layers,
the first ring power supply is connected to the first power supply source wire in at least one of the plurality of wire layers,
the second ring power supply is connected to the third power supply source wire in at least one of the plurality of wire layers,
the third power supply source IO terminal is connected to the third power supply source wire,
the first power supply source IO terminal and the third power supply source IO terminal in a pair are disposed outside the first ring power supply and the second ring power supply in a pair when viewed in plan, and
the wire layers of the first power supply source wire and the third power supply source wire are the same wire layer.
11. The semiconductor integrated circuit of claim 7 , further comprising:
a second ring power supply;
a third power supply source wire; and
a third power supply source IO terminal, wherein:
each of the first ring power supply and the second ring power supply includes a plurality of wire layers,
the first ring power supply is connected to the first power supply source wire in at least one of the plurality of wire layers,
the second ring power supply is connected to the third power supply source wire in at least one of the plurality of wire layers,
the third power supply source IO terminal is connected to the third power supply source wire,
the first power supply source IO terminal and the third power supply source IO terminal in a pair are disposed outside the first ring power supply and the second ring power supply in a pair when viewed in plan, and
the wire layers of the first power supply source wire and the third power supply source wire are the same wire layer.
12. The semiconductor integrated circuit of claim 4 , wherein
a total number of connection points of the first power supply source wire to the first ring power supply, connection points of the second power supply source wire to the first ring power supply, and connection points of the first branched wire to the first ring power supply is larger than a total number of the first power supply source IO terminal and the second power supply source IO terminal.
13. The semiconductor integrated circuit of claim 12 , wherein
the second power supply source wire includes a plurality of wire layers.
14. The semiconductor integrated circuit of claim 13 , further comprising:
a second ring power supply;
a third power supply source wire; and
a third power supply source IO terminal, wherein:
each of the first ring power supply and the second ring power supply includes a plurality of wire layers,
the first ring power supply is connected to the first power supply source wire in at least one of the plurality of wire layers,
the second ring power supply is connected to the third power supply source wire in at least one of the plurality of wire layers,
the third power supply source IO terminal is connected to the third power supply source wire,
the first power supply source IO terminal and the third power supply source IO terminal in a pair are disposed outside the first ring power supply and the second ring power supply in a pair when viewed in plan, and
the wire layers of the first power supply source wire and the third power supply source wire are the same wire layer.
15. The semiconductor integrated circuit of claim 12 , wherein:
the first power supply source wire further includes a second branched wire, and
the second power supply source wire is connected to the second branched wire.
16. The semiconductor integrated circuit of claim 15 , wherein
each of the second power supply source wire and the second branched wire includes a plurality of wire layers.
17. The semiconductor integrated circuit of claim 16 , further comprising:
a second ring power supply;
a third power supply source wire; and
a third power supply source IO terminal, wherein:
each of the first ring power supply and the second ring power supply includes a plurality of wire layers,
the first ring power supply is connected to the first power supply source wire in at least one of the plurality of wire layers,
the second ring power supply is connected to the third power supply source wire in at least one of the plurality of wire layers,
the third power supply source IO terminal is connected to the third power supply source wire,
the first power supply source IO terminal and the third power supply source IO terminal in a pair are disposed outside the first ring power supply and the second ring power supply in a pair when viewed in plan, and
the wire layers of the first power supply source wire and the third power supply source wire are the same wire layer.
18. The semiconductor integrated circuit of claim 15 , further comprising:
a second ring power supply;
a third power supply source wire; and
a third power supply source IO terminal, wherein:
each of the first ring power supply and the second ring power supply includes a plurality of wire layers,
the first ring power supply is connected to the first power supply source wire in at least one of the plurality of wire layers,
the second ring power supply is connected to the third power supply source wire in at least one of the plurality of wire layers,
the third power supply source IO terminal is connected to the third power supply source wire,
the first power supply source IO terminal and the third power supply source IO terminal in a pair are disposed outside the first ring power supply and the second ring power supply in a pair when viewed in plan, and
the wire layers of the first power supply source wire and the third power supply source wire are the same wire layer.
19. The semiconductor integrated circuit of claim 12 , further comprising:
a second ring power supply;
a third power supply source wire; and
a third power supply source IO terminal, wherein:
each of the first ring power supply and the second ring power supply includes a plurality of wire layers,
the first ring power supply is connected to the first power supply source wire in at least one of the plurality of wire layers,
the second ring power supply is connected to the third power supply source wire in at least one of the plurality of wire layers,
the third power supply source IO terminal is connected to the third power supply source wire,
the first power supply source IO terminal and the third power supply source IO terminal in a pair are disposed outside the first ring power supply and the second ring power supply in a pair when viewed in plan, and
the wire layers of the first power supply source wire and the third power supply source wire are the same wire layer.
20. The semiconductor integrated circuit of claim 1 , further comprising:
a second ring power supply;
a third power supply source wire; and
a third power supply source IO terminal, wherein:
each of the first ring power supply and the second ring power supply includes a plurality of wire layers,
the first ring power supply is connected to the first power supply source wire in at least one of the plurality of wire layers,
the second ring power supply is connected to the third power supply source wire in at least one of the plurality of wire layers,
the third power supply source IO terminal is connected to the third power supply source wire,
the first power supply source IO terminal and the third power supply source IO terminal in a pair are disposed outside the first ring power supply and the second ring power supply in a pair when viewed in plan, and
the wire layers of the first power supply source wire and the third power supply source wire are the same wire layer.