Semiconductor integrated circuit
View Patent ↗An integrated circuit includes: a first well of a first conductivity type; a second well of a second conductivity type coming into contact with the first well at a well boundary extending in a gate length direction; a first transistor having a first active region of the second conductivity type provided in the first well; and a second transistor which has a second active region of the second conductivity type provided in the first well and differing from the first active region in length in a gate width direction. The center location of the first active region in the gate width direction is aligned with the center location of the second active region in the gate width direction with reference to the well boundary.
1. A semiconductor integrated circuit comprising:
a first well region of a first conductivity type provided in a substrate;
a second well region of a second conductivity type provided in the substrate and coming into contact with the first well region at a well boundary extending in a gate length direction;
a first active region provided in the first well region and having first source and drain regions of the second conductivity type; and
a second active region provided in the first well region, having second source and drain regions of the second conductivity type, and differing in length in a gate width direction from the first active region,
wherein the distance from the well boundary to a halfway point of the length of the first active region in the gate width direction is substantially the same as the distance from the well boundary to a halfway point of the length of the second active region in the gate width direction.
2. The circuit of claim 1 ,
wherein the first active region has a greater length in the gate width direction than the second active region, and
the distance from the well boundary to an end of the first active region located closer to the well boundary is smaller than the distance from the well boundary to an end of the second active region located closer to the well boundary.
3. The circuit of claim 1 , further comprising:
a first gate electrode formed above the first active region with a first gate insulating film interposed therebetween; and
a second gate electrode formed above the second active region with a second gate insulating film interposed therebetween.
4. The circuit of claim 1 ,
wherein the second active region is spaced in the gate length direction from the first active region.
5. The circuit of claim 1 , further comprising:
a third active region provided in the second well region, arranged axisymmetrically with respect to the first active region with the well boundary used as an axis, and having third source and drain regions of the first conductivity type; and
a fourth active region provided in the second well region, arranged axisymmetrically with respect to the second active region with the well boundary used as an axis, and having fourth source and drain regions of the first conductivity type,
wherein the distance from the well boundary to a halfway point of the length of the third active region in the gate width direction is substantially the same as the distance from the well boundary to a halfway point of the length of the fourth active region in the gate width direction with reference to the well boundary.
6. The circuit of claim 5 ,
wherein the third active region has the same shape as the first active region, and
the fourth active region has the same shape as the second active region.
7. The circuit of claim 5 , further comprising:
a third gate electrode formed above the third active region with a third gate insulating film interposed therebetween; and
a fourth gate electrode formed above the fourth active region with a fourth gate insulating film interposed therebetween,
wherein the first and third gate electrodes are portions of an integrally-formed first gate interconnect, and
the second and fourth gate electrodes are portions of an integrally-formed second gate interconnect.
8. The circuit of claim 1 ,
wherein a cell including the first well region and the second well region is arranged two-dimensionally to constitute a cell array, and
the circuit further comprises a spacer cell arranged outside the cell array in alignment in the gate length direction and along either one side of the cell array extending in the gate width direction.
9. The circuit of claim 8 ,
wherein the spacer cell has a length in the gate length direction of 1.0 μm or more.
10. The circuit of claim 8 ,
wherein a dummy active region is provided in the spacer cell.
11. The circuit of claim 1 , further comprising a fifth active region provided in the first well region, having fifth source and drain regions of the second conductivity type, and differing in length in the gate width direction from the first and second active regions,
wherein the distance from the well boundary to a halfway point of the length of the fifth active region in the gate width direction is substantially the same as the distance from the well boundary to a halfway point of the length of the first active region in the gate width direction with reference to the well boundary.