Program correlation message generation for debug
View Patent ↗A data processing system and method includes a data processor and memory that are coupled to debug circuitry that generates debug messages including address translation trace messages. A memory management unit (MMU) includes a translation lookaside buffer (TLB) for implementing address translation to translate addresses between virtual and physical forms. The debug circuitry includes message generation circuitry coupled to the MMU for receiving notice when TLB entries are modified and generating both an address translation trace message and a corresponding program correlation message containing at least one of branch history information and instruction count information. The branch history information is a history of direct branch instructions that are executed and whether, when executed, the direct branch instructions were taken. The instruction count information is a count of one or more data processing instructions executed up to a point in time when a new TLB entry is established in the TLB.
1. A data processing system comprising:
a data processor for executing a plurality of data processing instructions;
a memory coupled to the data processor for storing and providing information to the data processor;
debug circuitry coupled to the data processor for generating debug messages including address translation trace messages;
a memory management unit coupled to the debug circuitry, data processor and the memory, the memory management unit comprising a translation lookaside buffer (TLB) for implementing address translation to translate addresses between virtual and physical forms, wherein:
the debug circuitry comprises:
message generation circuitry coupled to the memory management unit for receiving notice when TLB entries are modified and generating both an address translation trace message and a corresponding program correlation message containing at least one of branch history information and instruction count information, the branch history information comprising a history of direct branch instructions that are executed and whether, when executed, the direct branch instructions were taken, and the instruction count information being a count of one or more data processing instructions executed up to a point in time when a new TLB entry is established in the TLB.
2. The data processing system of claim 1 wherein the message generation circuitry provides the corresponding program correlation message before providing the address translation trace message.
3. The data processing system of claim 1 wherein the message generation circuitry detects a need to generate a second program correlation message at the same point in time due to an event other than modification of a TLB entry, and the message generation circuitry combines the program correlation message and the second program correlation message to form a merged program correlation message that contains the branch history information, the instruction count information and at least one field of merged information that is common to both the program correlation message and the second program correlation message.
4. The data processing system of claim 1 wherein the message generation circuitry compresses a length of the address translation trace message and replaces a portion of the address translation trace message that is removed by compression with at least one of branch history information and instruction count information of one or more data processing instructions executed up to the point in time when the new TLB entry is established in the TLB.
5. The data processing system of claim 1 wherein the corresponding program correlation message contains both branch history information and instruction count information.
6. The data processing system of claim 1 wherein the message generation circuitry receives notice from the memory management unit in response to performing a TLB write entry operation.
7. The data processing system of claim 1 wherein a debugger is coupled to the data processing system for receiving both the address translation trace message and the corresponding program correlation message from the debug circuitry, the data processing system being within an integrated circuit and the debugger being external to the integrated circuit.
8. A method comprising:
providing a data processor for executing a plurality of data processing instructions;
coupling a memory to the data processor for storing and providing information to the data processor;
coupling a memory management unit to the data processor and the memory, the memory management unit comprising a translation lookaside buffer (TLB) for implementing address translation to translate addresses between virtual and physical forms;
coupling debug circuitry to the data processor and memory management unit for generating debug messages including address translation trace messages, the debug circuitry receiving notice when TLB entries are modified and generating both an address translation trace message and a corresponding program correlation message containing at least one of branch history information and instruction count information, the branch history information comprising a history of direct branch instructions that are executed and whether, when executed, the direct branch instructions were taken, and the instruction count information being a count of one or more data processing instructions executed up to a point in time when a new TLB entry is established in the TLB.
9. The method of claim 8 further comprising:
providing the corresponding program correlation message before providing the address translation trace message.
10. The method of claim 8 further comprising:
detecting a need to generate a second program correlation message at a same point in time as generating the program correlation message due to an event other than modification of a TLB entry; and
combining the program correlation message and the second program correlation message to form a merged program correlation message that contains the branch history information, the instruction count information and at least one field of merged information that is common to both the program correlation message and the second program correlation message.
11. The method of claim 8 further comprising:
compressing a length of the address translation trace message and replacing a portion of the address translation trace message that is removed by compression with at least one of branch history information and instruction count information of one or more data processing instructions executed up to the point in time when the new TLB entry is established in the TLB.
12. The method of claim 8 further comprising:
forming the corresponding program correlation message contains both branch history information and instruction count information.
13. The method of claim 8 further comprising:
the memory management unit providing notice to the debug circuitry in response to performing a TLB write entry operation.
14. A data processing system comprising:
an instruction fetch unit for receiving and storing a plurality of data processing instructions;
an instruction decoder coupled to the instruction fetch unit for receiving the plurality of data processing instructions and decoding each of the plurality of data processing instructions;
an execution unit coupled to the instruction decoder for executing the plurality of data processing instructions;
a memory coupled to the instruction fetch unit and the execution unit for storing information from the execution unit and providing information to the instruction fetch unit;
debug circuitry coupled to the instruction fetch unit, the instruction decoder and the execution unit for generating debug messages including address translation trace messages;
a memory management unit coupled to the debug circuitry, data processor and the memory, the memory management unit comprising a translation lookaside buffer (TLB) for implementing address translation to translate addresses between virtual and physical forms, wherein:
the debug circuitry comprises:
message generation circuitry coupled to the memory management unit for receiving notice when TLB entries are modified and generating both an address translation trace message and a corresponding program correlation message containing at least one of branch history information and instruction count information, the branch history information comprising a history of direct branch instructions that are executed and whether, when executed, the direct branch instructions were taken, and the instruction count information being a count of one or more data processing instructions executed up to a point in time when a new TLB entry is established in the TLB.
15. The data processing system of claim 14 wherein the message generation circuitry provides the corresponding program correlation message before providing the address translation trace message.
16. The data processing system of claim 14 wherein the message generation circuitry detects a need to generate a second program correlation message at the same point in time due to an event other than modification of a TLB entry, and the message generation circuitry combines the program correlation message and the second program correlation message to form a merged program correlation message that contains the branch history information, the instruction count information and at least one field of merged information that is common to both the program correlation message and the second program correlation message.
17. The data processing system of claim 14 wherein the message generation circuitry compresses a length of the address translation trace message and replaces a portion of the address translation trace message that is removed by compression with at least one of branch history information and instruction count information of one or more data processing instructions executed up to the point in time when the new TLB entry is established in the TLB.
18. The data processing system of claim 14 wherein the corresponding program correlation message contains both branch history information and instruction count information.
19. The data processing system of claim 14 wherein the message generation circuitry receives notice from the memory management unit in response to performing a TLB write entry operation.
20. The data processing system of claim 14 wherein a debugger is coupled to the data processing system for receiving both the address translation trace message and the corresponding program correlation message from the debug circuitry, the data processing system being within an integrated circuit and the debugger being external to the integrated circuit.