Device selection schemes in multi chip package NAND flash memory system
View Patent ↗Device selection schemes in multi-chip package NAND flash memory systems are provided. A memory system is provided that has a memory controller, and a number of memory devices connected to the controller via a common bus with a multi-drop connection. The memory controller performs device selection by command. A corresponding memory controller is provided which performs device selection by command. Alternatively, device selection is performed by address. A memory device is provided use in memory system comprising a memory controller, and a number of memory devices inclusive of the memory device connected to the controller via a common bus with a multi-drop connection. The memory device has a register containing a device identifier, and a device identifier comparator that compares selected bits of a received input address to contents of the register to determine if there is a match. The memory device is selected if the device identifier comparator determines there is a match.
1. A memory system comprising:
a memory controller; and
a plurality of memory devices connected to the memory controller via a common bus with a multi-drop connection, each memory device composing a burst data controller that, when a device identifier of the memory device matches a selected portion of a received input address, causes the memory device to be selected while a command input is in progress and while an address input is in progress,
wherein:
the memory controller is configured to perform device selection by the command comprising a command op code portion and the device identifier portion that together form not more than one byte of the command,
the plurality of memory devices comprises a plurality of NAND flash devices,
each of the NAND flash devices comprises a NAND memory cell array,
the NAND memory cell array is subdivided into blocks, and each block of the blocks is further subdivided into pages, and each page of the pages comprises a j-byte data storage region and a k-byte spare field.
2. The memory system of claim 1 , wherein the memory controller is configured to perform device selection by command by, for each command, transmitting the command; and
wherein each of the plurality of memory devices acts upon the command when the device identifier portion of the command matches a device identifier of the memory device.
3. The memory system of claim 1 wherein the command is a command selected from the following:
for a read status operation for a device having device identifier <device_ID>: <read op_code>; <device_ID>, where <read op_code> is an op code specifying read operation; for a burst read operation for a device having device identifier <device_ID>: <burst read op_code>; <device_ID>, where <burst read op_code> is an op code specifying burst read operation;
for a block erase operation for a device having device identifier <device_ID>: <block erase op_code>; <device_ID>, where <block erase op_code> is an op code specifying block erase operation;
for a read operation for a device having device identifier <device_ID>: <read status op_code>; <device_ID>, where <read status op_code> is an op code specifying read status operation;
for a page program operation for a device having device identifier <device_ID>: <page program op_code>; <device_ID>, where <page program op_code> is an op code specifying page program operation.
4. The memory system of claim 1 wherein the command is an 8 bit command, of which the command op code portion is 4 bits and the device identifier portion is 4 bits.
5. The memory system of claim 1 wherein device selection is performable by command with device interleave operations.
6. The memory system of claim 5 wherein the interleave operation comprises one of:
page program of a first device interleaved with page program of a second device;
page program of a first device interleaved with page read of a second device;
page read of a first device interleaved with page read of a second device.
7. The memory system of claim 1 wherein the plurality of NAND flash devices are part of a multi-chip package.
8. The memory system of claim 7 comprising:
a common chip enable for the plurality of NAND flash devices.
9. The memory system of claim 1 wherein the common bus comprises:
a write protect line;
a write enable line;
a read enable line;
an address latch enable line;
a command latch enable line;
a chip enable line;
an I/O for command, address and data; and
a ready/busy line.
10. A memory system comprising:
a memory controller;
a plurality of memory devices connected to the controller via a common bus with a multi-drop connection, each memory device comprising a burst data controller that, when a device identifier of the memory device matches a selected portion of a received input address, causes the memory device to be selected while a command input is in progress and while an address input is in progress, wherein the plurality of memory devices comprises a plurality of NAND flash devices that are part of a multi-chip package, and the common bus includes a plurality of I/O lines; and
a common chip enable for the plurality of NAND flash devices, and
wherein:
the memory controller is configured to perform device selection according to the command,
each of the NAND flash devices comprises a NAND memory cell array,
the NAND memory cell array is subdivided into blocks, and each block of the blocks is further subdivided into pages, and each page of the pages comprises a j-byte data storage region and a k-byte spare field.
11. The memory system of claim 10 wherein the memory system is configured to communicate with a main system via the memory controller.
12. The memory system of claim 10 wherein the memory system is configured to communicate with a processor via the memory controller.