Phase detection in a sync pulse generator

1. A phase detector operable with a first clock signal and a second clock signal, said first and second clock signals having a ratio of N first clock cycles to M second clock cycles, where N/M≧1, comprising:

at least one first flip flop operable to sample said first clock signal with a rising edge of said second clock signal, said at least one first flip flop thereby operating to assert a first sampled clock signal having a zero-to-one transition therein that is indicative of coincident rising edges in said first and second clock signals; and

at least one second flip flop operable to sample said first clock signal with a falling edge of said second clock signal, said at least one second flip flop operating to assert a second sampled clock signal having a one-to-zero transition therein that is indicative of coincident rising edges in said first and second clock signals, wherein said first and second sampled clock signals are operable to be forwarded to validation circuitry for validating said coincident rising edges based upon skew tolerance between said first and second clock signals and to generate a valid edge signal responsive thereto.

2. The phase detector as recited in claim 1 , wherein said at least one first flip flop comprises two flip flops operable to sample said first clock signal with a rising edge of said second clock signal.

3. The phase detector as recited in claim 1 , wherein said at least one second flip flop comprises two flip flops operable to sample said first clock signal with a falling edge of said second clock signal.

4. The phase detector as recited in claim 1 , wherein each of said first and second sampled clock signals is operable to be staged via a delay register portion.

5. The phase detector as recited in claim 1 , wherein said first clock signal is a link clock signal operable in a computer system.

6. The phase detector as recited in claim 1 , wherein said second clock signal is a core clock signal operable in a computer system.

7. The phase detector as recited in claim 1 , wherein said ratio of N:M cycles comprises a 5:4 ratio of link-to-core clock signals operable in a computer system.

8. The phase detector as recited in claim 1 , wherein said ratio of N:M cycles comprises a 4:3 ratio of link-to-core clock signals operable in a computer system.

9. A phase detection method operable with a first clock signal and a second clock signal, said first and second clock signals having a ratio of N first clock cycles to M second clock cycles, where N/M≧1, comprising:

sampling said first clock signal with a rising edge of said second clock signal to assert a first sampled clock signal having a zero-to-one transition therein that is indicative of coincident rising edges in said first and second clock signals;

sampling said first clock signal with a falling edge of said second clock signal to assert a second sampled clock signal having a one-to-zero transition therein that is indicative of coincident rising edges in said first and second clock signals; and

forwarding at least one of said first and second sampled clock signals indicative of coincident rising edges to validation circuitry, said validation circuitry for validating said coincident rising edges based upon skew tolerance between said first and second clock signals and to generate a valid edge signal responsive thereto.

10. The method as recited in claim 9 , wherein the operation of sampling said first clock signal with a rising edge of said second clock signal comprises sampling a link clock signal with a rising edge of a core clock signal.

11. The method as recited in claim 9 , wherein the operation of sampling said first clock signal with a falling edge of said second clock signal comprises sampling a link clock signal with a falling edge of a core clock signal.

12. The method as recited in claim 9 , further comprising the operation of staging each of said first and second sampled clock signals via at least one delay register.

13. The method as recited in claim 9 , wherein said ratio of N:M cycles comprises a 5:4 ratio of link-to-core clock signals operable in a computer system.

14. The method as recited in claim 9 , wherein said ratio of N:M cycles comprises a 4:3 ratio of link-to-core clock signals operable in a computer system.

15. A phase detection system operable with a first clock signal and a second clock signal having a ratio of N first clock cycles to M second clock cycles, where N/M≧1, comprising:

means for sampling said first clock signal with a rising edge of said second clock signal to assert a first sampled clock signal having a zero-to-one transition therein that is indicative of coincident rising edges in said first and second clock signals; and

means for sampling said first clock signal with a falling edge of said second clock signal to assert a second sampled clock signal having a one-to-zero transition therein that is indicative of coincident rising edges in said first and second clock signals, wherein at least one of said first and second sampled clock signals indicative of coincident rising edges is operable to be forwarded to validation circuitry, said validation circuitry for validating said coincident rising edges based upon skew tolerance between said first and second clock signals and to generate a valid edge signal responsive thereto.

16. The phase detection system as recited in claim 15 , wherein said means for sampling said first clock signal with a rising edge of said second clock signal further comprises means for sampling a link clock signal with a rising edge of a core clock signal.

17. The phase detection system as recited in claim 15 , wherein said means for sampling said first clock signal with a falling edge of said second clock signal further comprises means for sampling a link clock signal with a falling edge of a core clock signal.

18. The phase detection system as recited in claim 15 , further comprising means for delaying each of said first and second sampled clock signals by a predetermined amount.

19. The phase detection system as recited in claim 15 , wherein said ratio of N:M cycles comprises a 5:4 ratio of link-to-core clock signals operable in a computer system.

20. The phase detection system as recited in claim 15 , wherein said ratio of N:M cycles comprises a 4:3 ratio of link-to-core clock signals operable in a computer system.

21. An apparatus operable with a first clock signal and a second clock signal, comprising:

at least one first flip flop operable to sample said first clock signal with a rising edge of said second clock signal to generate a first sampled clock signal; and

at least one second flip flop operable to sample said first clock signal with a falling edge of said second clock signal to generate a second sampled clock signal, said sampling by said at least one first and one second flip flops producing transitions in said first and second sampled clock signals indicative of coincident edges between said first and second clock signals, wherein at least one of said first and second sampled clock signals indicative of coincident rising edges is operable to be forwarded to validation circuitry, said validation circuitry for validating said coincident rising edges based upon skew tolerance between said first and second clock signals and to generate a valid edge signal responsive thereto.

22. The apparatus as recited in claim 21 , wherein said coincident edges comprise coincident rising edges.

23. The apparatus as recited in claim 21 , wherein said coincident edges comprise coincident falling edges.

24. The apparatus as recited in claim 21 , wherein said first clock signal is a link clock signal operable in a computer system.

25. The apparatus as recited in claim 21 , wherein said second clock signal is a core clock signal operable in a computer system.

26. The apparatus as recited in claim 21 , wherein said first clock signal and said second clock signal define a 5:4 ratio of link-to-core clock signals operable in a computer system.

27. The apparatus as recited in claim 21 , wherein said first clock signal and said second clock signal define a 4:3 ratio of link-to-core clock signals operable in a computer system.