Low leakage and data retention circuitry
View Patent ↗An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.
1. An integrated circuit comprising:
a plurality of power islands having associated power consumptions capable of being dynamically changed, each of the power islands including circuitries and sleep transistors in coupled relation with the circuitries; and
a sleep generator in communication with at least one of the power islands to provide a variable voltage, and
the sleep transistors being included within the integrated circuit to facilitate reduction of power consumed by the circuitries, and the sleep transistors being configured to receive the variable voltage that is:
i) generated by the sleep generator based on a control signal receivable from an adaptive leakage controller; and
ii) changed under control of the adaptive leakage controller.
2. The integrated circuit as claimed in claim 1 wherein the at least one of the power islands can be put to sleep and taken out of sleep at different times.
3. The integrated circuit as claimed in claim 2 wherein the sleep generator is within a power island manager that includes a state machine to control when the at least one of the power islands is put to sleep and when the at least one of the power islands is taken out of sleep.
4. The integrated circuit as claimed in claim 1 wherein the power islands are delineated based on functional intellectual property units of the integrated circuit.
5. The integrated circuit as claimed in claim 1 wherein the power islands are delineated by memory, logic and third party intellectual property.
6. The integrated circuit as claimed in claim 1 wherein the variable voltage is an optimum voltage.
7. The integrated circuit as claimed in claim 6 wherein the optimum voltage is dependent upon both process variation and temperature variation.
8. The integrated circuit as claimed in claim 1 wherein the sleep generator comprises a charge pump.
9. The integrated circuit as claimed in claim 1 wherein the control signal is a digital signal.
10. A method carried out in an integrated circuit that includes an adaptive leakage controller and a plurality of power islands, each power island of the plurality of power islands including circuitries and sleep transistors in coupled relation with the circuitries, and the method comprising:
generating a variable voltage based on a control signal received from the adaptive leakage controller;
providing the variable voltage to at least one of the power islands;
receiving the variable voltage at the sleep transistors to facilitate reduction of power consumed by the circuitries; and
dynamically changing, under control of the adaptive leakage controller, the variable voltage.
11. The method as claimed in claim 10 further comprising putting to sleep and taking out of sleep, at different times, the at least one of the power islands.
12. The method as claimed in claim 11 wherein the putting to sleep and the taking out of sleep is controlled by a state machine.
13. The method as claimed in claim 10 wherein the variable voltage is an optimum voltage.
14. The method as claimed in claim 13 wherein the optimum voltage is dependent upon both process variation and temperature variation.
15. The method as claimed in claim 13 wherein the optimum voltage is generated by a charge pump.
16. The method as claimed in claim 10 wherein the control signal is a digital signal.