Non-volatile memory device having configurable page size
View Patent ↗A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted.
1. A flash memory device, comprising:
a memory bank comprising a plurality of planes each having a page buffer for storing write data for programming to a corresponding plane, the plurality of planes being organized into a plurality of tiles each including two planes coupled to a shared row decoder for driving wordlines in each of the two planes; and
a page size configurator operable to selectively enable, at the same time, at least a first plane of a first tile and a second plane of a second tile.
2. The flash memory device of claim 1 , wherein the page size configurator selectively enables the first and second planes when required based on received page size configuration data and address data.
3. The flash memory device of claim 1 , wherein the shared row decoder of each of the tiles is operable to selectively drive wordlines of at least one of the two planes in response to row decoder enabling signals.
4. The flash memory device of claim 3 , wherein the shared row decoder comprises:
a row driver for selectively passing row drive signals to the wordlines of the one of the two planes in response to a first output voltage, and to the wordlines of the other of the two planes in response to a second output voltage; and
a block decoder for selectively providing a master output voltage as the first output voltage and the second output voltage in response to the row decoder enabling signals.
5. The flash memory device of claim 4 , wherein the page size configurator comprises:
one or more plane selectors operable to provide the row decoder enabling signals to corresponding shared row decoders in response to plane enabling signals and a tile enabling signal; and
a configuration decoder operable to decode a plane address to provide the plane enabling signals and for decoding a tile address to provide the tile enabling signal, the plane enabling signals and the tile enabling signal having logic levels configurable in response to page size configuration data.
6. The flash memory device of claim 5 , wherein the page size configurator further includes a configuration register for storing the page size configuration data.
7. The flash memory device of claim 5 , wherein each of the one or more plane selectors decodes the same plane enabling signals and different tile enabling signals.
8. The flash memory device of claim 7 , wherein the configuration decoder comprises:
a plane decoding circuit enabled by a first bit of the page size configuration data for decoding the plane address and for driving one of the plane enabling signals to an active logic level; and
a tile decoding circuit enabled by a second bit of the page size configuration data for decoding the tile address and for driving one of the tile enabling signals to an active logic level.
9. The flash memory device of claim 8 , wherein the plane decoding circuit drives both the plane enabling signals to the active logic level when disabled by the first bit of the page size configuration data, and the tile decoding circuit drives both the tile enabling signals to the active logic level when disabled by the second bit of the page size configuration data.
10. The flash memory device of claim 5 , wherein each of the one or more plane selectors decodes different pairs of plane enabling signals and different tile enabling signals.
11. The flash memory device of claim 10 , wherein the configuration decoder comprises:
one or more plane decoding circuits each operable to:
receive one bit of the page size configuration data for decoding the plane address; and
drive one plane enabling signal of each of the different pairs of plane enabling signals to an active logic level when enabled by the corresponding one bit of the page size configuration data; and
a tile decoding circuit operable to:
decode the tile address; and
drive one of the tile enabling signals to an active logic level when enabled by another bit of the page size configuration data.
12. The flash memory device of claim 1 , wherein the plurality of tiles comprises N tiles, where N is an integer number greater than 1.
13. The flash memory device of claim 12 , wherein the page size configurator comprises:
N plane selectors for providing N pairs of row decoder enabling signals to corresponding N shared row decoders in response to plane enabling signals and N tile enabling signals; and
a configuration decoder for decoding a plane address to provide the plane enabling signals and for decoding a tile address to provide the N tile enabling signals, the plane enabling signals and the N tile enabling signals having logic levels configurable in response to page size configuration data.
14. The flash memory device of claim 13 , wherein the configuration decoder comprises:
one plane decoding circuit enabled by a first bit of the page size configuration data for decoding the plane address and driving one of the plane enabling signals to an active logic level, each of the N plane selectors receiving the same plane enabling signals, and
a tile decoding circuit enabled by a second bit of the page size configuration data for decoding the tile address and driving one of the N tile enabling signals to an active logic level.
15. The flash memory device of claim 13 , wherein the plane enabling signals include N pairs of plane enabling signals, and the configuration decoder provides:
N plane decoding circuits each operable to:
decode the plane address; and
drive one of the N pairs of plane enabling signals to an active logic level when enabled by a corresponding bit of the page size configuration data, each of the N plane selectors receiving one of the N pairs of plane enabling signals; and
a tile decoding circuit operable to:
decode the tile address; and
drive one of the N tile enabling signals to an active logic level when enabled by another bit of the page size configuration data.
16. A system, comprising:
a controller operable to generate one or more control signals; and
a flash memory device communicatively coupled to the controller and operable to receive the one or more control signals, the flash memory device comprising:
a memory bank comprising a plurality of planes each having a page buffer for storing write data for programming to a corresponding plane, the plurality of planes being organized into a plurality of tiles each including two planes coupled to a shared row decoder for driving wordlines in each of the two planes; and
a page size configurator operable to selectively enable, at the same time, at least a first plane of a first tile and a second plane of a second tile in response to the one or more control signals.
17. The system of claim 16 , wherein the page size configurator selectively enables the first and second planes when required in response to page size configuration data and address data generated based on the received control signals.
18. The system of claim 16 , wherein the shared row decoder of each of the tiles is operable to selectively drive wordlines of at least one of the two planes in response to row decoder enabling signals.
19. The system of claim 18 , wherein the shared row decoder comprises:
a row driver for selectively passing row drive signals to the wordlines of the one of the two planes in response to a first output voltage, and to the wordlines of the other of the two planes in response to a second output voltage; and
a block decoder for selectively providing a master output voltage as the first output voltage and the second output voltage in response to the row decoder enabling signals.
20. The system of claim 19 , wherein the page size configurator comprises:
one or more plane selectors operable to provide the row decoder enabling signals to corresponding shared row decoders in response to plane enabling signals and a tile enabling signal; and
a configuration decoder operable to decode a plane address to provide the plane enabling signals and for decoding a tile address to provide the tile enabling signal, the plane enabling signals and the tile enabling signal having logic levels configurable in response to page size configuration data.
21. The system of claim 20 , wherein the page size configurator further includes a configuration register for storing the page size configuration data.
22. The system of claim 20 , wherein each of the one or more plane selectors decodes the same plane enabling signals and different tile enabling signals.
23. The system of claim 22 , wherein the configuration decoder comprises:
a plane decoding circuit enabled by a first bit of the page size configuration data for decoding the plane address and for driving one of the plane enabling signals to an active logic level; and
a tile decoding circuit enabled by a second bit of the page size configuration data for decoding the tile address and for driving one of the tile enabling signals to an active logic level.
24. The system of claim 23 , wherein the plane decoding circuit drives both the plane enabling signals to the active logic level when disabled by the first bit of the page size configuration data, and the tile decoding circuit drives both the tile enabling signals to the active logic level when disabled by the second bit of the page size configuration data.
25. The system of claim 20 , wherein each of the one or more plane selectors decodes different pairs of plane enabling signals and different tile enabling signals.
26. The system of claim 25 , wherein the configuration decoder comprises:
one or more plane decoding circuits each operable to:
receive one bit of the page size configuration data for decoding the plane address; and
drive one plane enabling signal of each of the different pairs of plane enabling signals to an active logic level when enabled by the corresponding one bit of the page size configuration data; and
a tile decoding circuit operable to:
decode the tile address; and
drive one of the tile enabling signals to an active logic level when enabled by another bit of the page size configuration data.
27. A flash memory device, comprising:
a memory bank comprising a first plane and a second plane, the first plane and second plane each having:
a page buffer for storing write data for programming to a corresponding plane; and
a dedicated row decoder for driving wordlines of a corresponding plane, at least a first wordline of the first plane and a second wordline of the second plane being selectively enabled at the same time, the first wordline being different than the second wordline.
28. A system, comprising:
a controller operable to generate one or more control signals; and
a flash memory device communicatively coupled to the controller and operable to receive the one or more control signals, the flash memory device comprising:
a memory bank comprising a first plane and a second plane, the first plane and second plane each having:
a page buffer for storing write data for programming to a corresponding plane; and
a dedicated row decoder for driving wordlines of a corresponding plane, at least a first wordline of the first plane and a second wordline of the second plane being selectively enabled at the same time in response to the one or more control signals, the first wordline being different than the second wordline.