Data storage and stackable chip configurations
View Patent ↗A first memory device and second memory device have a same input/output layout configuration. To form a stack, the second memory device is secured to the first memory device. To facilitate connectivity, the second memory device is rotationally offset with respect to the first memory device in the stack to align outputs of the first memory device with corresponding inputs of the second memory device. The rotational offset of the second memory device with respect to the first memory device aligns one or more outputs of the first memory device with one or more respective inputs of the second memory device. Based on links between outputs and inputs from one memory device to another in the stack, the stack of memory devices can include paths facilitating one or more series connection configurations through the memory devices.
1. A system comprising:
a first memory device for storing data;
a second memory device for storing data, the second memory device having a same input/output layout configuration as the first memory device;
a stack including the second memory device secured to the first memory device, the second memory device rotated 180 degrees with respect to the first memory device such that outputs of the first memory device are positioned adjacent to corresponding inputs to the second memory device; and
connectivity between the outputs of the first memory device and the inputs of the second memory device, the connectivity including connections between surface pads on a plane of the first memory device and through-holes of the second memory device.
2. The system as in claim 1 , wherein the surface pads are outputs of the first memory device and the through-holes are inputs to the second memory device.
3. The system as in claim 1 , wherein the first memory device is rotated perpendicular to the second memory device.
4. The system as in claim 1 , wherein the connectivity includes a first connection and a second connection, the first connection linking a first surface pad of the first memory device to a first though-hole of the second memory device, the second connection linking a second surface pad of the first memory device to a second through-hole of the second memory device.
5. The system as in claim 4 , wherein the connectivity forms paths to convey data through the stack of memory devices, the first connection creating a first path by linking a first output of the first memory device to a first input of the second memory device, the second connection creating a second path by linking a second output of the first memory device to a second input of the second memory device.
6. The system as in claim 1 , wherein the stack includes a third memory device secured to the second memory device, the third memory device having the same input/output layout configuration as the first memory device and the second memory device, the system further comprising:
connectivity between outputs of the second memory device and inputs of the third memory device, the connectivity including connections between surface pads on a plane of the second memory device and through-holes of the third memory device.
7. The system as in claim 6 , wherein the surface pads on the plane of the second memory device are outputs of the second memory device and the through-holes of the third memory device are inputs.
8. The system as in claim 1 , wherein the second memory device is rotated with respect to the first memory device from a position in which the same input/output layout configurations of the first memory device and the second memory device are aligned with each other.
9. The system as in claim 1 , wherein the connections between surface pads on a plane of the first memory device and through-holes of the second memory device are formed without wiring.