Memory system and method using stacked memory device dice
View Patent ↗A method and apparatus for organizing memory for a computer system including a plurality of memory devices 2, 3 , connected to a logic device 1 , particularly a memory system having a plurality of stacked memory dice connected to a logic die, with the logic device 1 having capability to analyze and compensate for differing delays to the stacked devices 2,3,4,5 stacking multiple dice divided into partitions serviced by multiple buses 21,22 connected to a logic die 1 , to increase throughput between the devices 2,3 and logic 1 device allowing large scale integration of memory with self-healing capability.
1. A memory device for use in computer systems, comprising:
a plurality of semiconductor dies stacked and connected together, each of the dies comprising a plurality of partitions; and,
a plurality of vaults each comprising a grouping of the partitions in one of the dies, the number of partitions in each vault being the same as the number of stacked semiconductor dies.
2. The memory device for use in computer systems as in claim 1 , further comprising switch circuits configured to form the vaults.
3. The memory device for use in computer systems as in claim 2 , wherein the switch circuits are located on the dies.
4. The memory device for use in computer systems as in claim 1 , further comprising a logic dice connected to each of the dies by at least one wide bus.
5. The memory device for use in computer systems as in claim 4 , wherein the logic dice is configured to analyze and compensate for differing delays to the stacked memory dies.
6. The memory device for use in computer systems as in claim 4 , further comprising switch circuits configured to form the vaults.
7. The memory device for use in computer systems as in claim 4 , wherein each of the dies further comprise switch circuits connected to the logic dice.
8. A method for organizing memory for use in computer systems, comprising:
stacking a plurality of semiconductor memory dies each having a plurality of memory cells;
partitioning each die into a plurality of vaults each having a plurality of cells, the number of partitions in each vault being the same as the number of stacked semiconductor dies; and
connecting the vaults to a logic die with wide busses, the connection to vaults being switched with a switching signal.
9. The method for organizing memory for use in computer systems as in claim 8 , wherein the switching signal originates from the logic die and each die is provided with a plurality of switches responsive to the switching signal.
10. The method for organizing memory for use in computer systems as in claim 8 , wherein the wide busses are Through Silicon Vias (TSVs).
11. The method for organizing memory for use in computer systems as in claim 8 , further comprising reallocating vaults from one wide bus to another wide bus in the event of a malfunction in the one wide bus.
12. The method for organizing memory for use in computer systems as in claim 8 wherein the switching signal is configured to provide a data valid period of separate memory device dice each have the same timing.
13. The method for organizing memory for use in computer systems as in claim 9 , wherein the switching signal is configured to provide a maximum valid data period.
14. The method for organizing memory for use in computer systems as in claim 13 , wherein the switching signal is selectively delayed to some dies to provide a maximum valid data period.
15. The method for organizing memory for use in computer systems as in claim 8 , wherein the switching signal is a RDQS signal sent to each of memory device dice having timing adjustment circuits for each RDQS.
16. The method for organizing memory for use in computer systems as in claim 15 , wherein each memory device dice output data synchronized to their RDQS.
17. The method for organizing memory for use in computer systems as in claim 16 , wherein the RDQS signal adjusts RDQS timing so that data valid period of memory device dice have same timing.
18. The method for organizing memory for use in computer systems as in claim 17 , wherein the RDQS signal changes when supply voltage and temperature change while memory device dice are working to update the timing of data valid period continuously.