CPU with stacked memory
View Patent ↗A multi-chip package has a substrate with electrical contacts for connection to an external device. A CPU die is disposed on the substrate and is in communication with the substrate. The CPU die has a plurality of processor cores occupying a first area of the CPU die, and an SRAM cache occupying a second area of the CPU die. A DRAM cache is disposed on the CPU die and is in communication with the CPU die. The DRAM cache has a plurality of stacked DRAM die. The plurality of stacked DRAM dies are substantially aligned with the second area of the CPU die, and substantially do not overlap the first area of the CPU die. A multi-chip package having a DRAM cache disposed on the substrate and a CPU die disposed on the DRAM cache is also disclosed.
1. A multi-chip package comprising:
a substrate having electrical contacts for connection to an external device;
a CPU die disposed on the substrate and being in communication with the substrate; the CPU die comprising:
a plurality of processor cores occupying a first area of the CPU die; and
an SRAM cache occupying a second area of the CPU die; and
a DRAM cache disposed on the CPU die and being in communication with the CPU die,
the DRAM cache comprising a plurality of stacked DRAM dies,
the plurality of stacked DRAM dies being substantially aligned with the second area of the CPU die; and
the plurality of stacked DRAM dies substantially not overlapping the first area of the CPU die.
2. The multi-chip package of claim 1 , further comprising:
a bulk material disposed on the CPU die and being substantially aligned with the first area of the CPU die.
3. The multi-chip package of claim 2 , wherein:
the bulk material has a top surface substantially coplanar to a top surface of the plurality of stacked DRAM dies.
4. The multi-chip package of claim 3 , further comprising a heat sink disposed on the top surface of the bulk material and on the top surface of the plurality of stacked DRAM dies.
5. The multi-chip package of claim 2 , further comprising a heat sink disposed on a top surface of the bulk material.
6. The multi-chip package of claim 3 , further comprising:
a chip disposed on the top surface of the bulk material and on the top surface of the plurality of stacked DRAM dies, the chip being in communication with the CPU die.
7. The multi-chip package of claim 6 , wherein:
the chip and the plurality of DRAM dies are in communication with the CPU die via through-silicon vias (TSVs).
8. The multi-chip package of claim 7 , wherein at least some of the TSVs pass through the bulk material.
9. The multi-chip package of claim 1 , further comprising a heat sink disposed on a top surface of the plurality of stacked DRAM dies.
10. The multi-chip package of claim 1 , further comprising a heat sink disposed on a top surface of the first area of the CPU die.
11. The multi-chip package of claim 1 , further comprising at least one die disposed on the CPU die and being substantially aligned with the first area of the CPU die, the at least one die comprising at least one additional processor core.
12. A multi-chip package comprising:
a substrate having electrical contacts for connection to an external device;
a DRAM cache disposed on the substrate and being in communication with a CPU die, the DRAM cache comprising a plurality of stacked DRAM dies;
a bulk material disposed on the substrate; and
the CPU die being disposed on the DRAM cache and the substrate, the CPU die being in communication with the substrate; the CPU die comprising:
a plurality of processor cores occupying a first area of the CPU die; and
an SRAM cache occupying a second area of the CPU die,
the plurality of stacked DRAM dies being substantially aligned with the second area of the CPU die; and
the bulk material being substantially aligned with the first area of the CPU die.
13. The multi-chip package of claim 12 , wherein:
the bulk material has a top surface substantially coplanar to a top surface of the plurality of stacked DRAM dies.
14. The multi-chip package of claim 12 , wherein:
the substrate and the plurality of DRAM dies are in communication with the CPU die via through-silicon vias (TSVs).
15. The multi-chip package of claim 14 , wherein at least some of the TSVs pass through the bulk material.
16. The multi-chip package of claim 12 , further comprising a heat sink disposed on a top surface of the CPU die.
17. The multi-chip package of claim 12 , further comprising at least one die disposed on a top surface of the bulk material and being substantially aligned with the first area of the CPU die, the at least one die comprising at least one additional processor core.