HIERARCHICAL COMMON SOURCE LINE STRUCTURE IN NAND FLASH MEMORY
Each memory cell string in a generic NAND flash cell block connects to a Common Source Line (CLS). A value for applying to the CSL is centrally generated and distributed to a local switch logic unit corresponding to each NAND flash cell block. For source-line page programming, the distribution line may be called a Global Common Source Line (GCSL). In an array of NAND flash cell blocks, only one NAND flash cell block is selected at a time for programming. To reduce power consumption, only the selected NAND flash cell block receives a value on the CSL that is indicative of the value on the GCSL. Additionally, the CSLs of non-selected NAND flash cell blocks may be disabled through an active connection to ground.
1 . A method of reducing power consumption from source-line page programming in a block of NAND flash memory strings, said NAND flash memory strings connected to a local common source line, said method comprising:
receiving an indication of selection of said block of NAND flash memory strings;
responsive to receiving said indication of selection, permitting passage of a signal received on a global common source line to said block of NAND flash memory strings on said local common source line;
receiving an enable indication; and
responsive to receiving said enable indication, isolating said local common source line from a predetermined voltage being ground.
2 . A memory array comprising:
a NAND flash cell block, said NAND flash cell block including a plurality of NAND flash memory strings, each NAND flash memory string of said plurality of NAND flash memory strings connected to a local common source line;
a local switch logic unit including:
a first semiconductor switch for selectively allowing passage, on said local common source line, of a signal to said plurality of NAND flash memory strings in said NAND flash cell block, wherein said signal is received on a global common source line; and
a second semiconductor switch for selectively placing a predetermined voltage on said local common source line,
wherein
the first semiconductor switch is an n-type Metal Oxide Semiconductor (NMOS) transistor;
second semiconductor switch is an n-type Metal Oxide Semiconductor (NMOS) transistor;
said local switch logic further comprises a first input line for receiving a voltage level indicative of selection of said NAND flash cell block; and
said predetermined voltage is ground.