Non-Volatile Semiconductor Memory with Page Erase
In a nonvolatile memory, less than a full block maybe erased as one or more pages. A select voltage is applied through pass transistors to each of plural selected wordlines and an unselect voltage is applied through pass transistor to each of plural unselected wordlines of a selected block. A substrate voltage is applied to the substrate of the selected block. A common select voltage may be applied to each selected wordline and the common unselect voltage may be applied to each unselected wordline. Select and unselect voltages may be applied to any of the wordlines of a select block. A page erase verify operation may be applied to a block having plural erased pages and plural nonerased pages.
1 . A method for erasing a page in a nonvolatile memory array having plural strings of memory cells on a substrate, wordlines across the strings to pages of memory cells and a pass transistor applying a voltage to each wordline, the method comprising:
enabling each pass transistors of a selected block; through a wordline decoder adapted to apply a select voltage to any of the pass transistors and to apply an unselected voltage to any other of the pass transistors:
at each of plural selected wordlines of the selected block, applying the select voltage to the pass transistor; and
at each of plural unselected wordlines of the selected block, applying the unselect voltage to the pass transistor; and
applying a substrate voltage to the substrate of the selected block, the voltage difference between the substrate voltage and a resulting voltage of each selected wordline causing the page of memory cells of the selected wordline to erase, and the voltage difference between the substrate voltage and a resulting voltage of each unselected wordline being less than that which erases the page of memory cells of the unselected wordline.
2 . The method of claim 1 wherein:
the selected wordlines include selected wordlines separated by at least one unselected wordline;
the unselected wordlines include unselected wordlines separated by at least one selected wordline;
the resulting voltage of each selected wordline is substantially the same as the select voltage and the resulting voltage of each unselected wordline is substantially the same as the unselect voltage or a floating voltage coupled from the unselect voltage toward the substrate voltage.
3 . The method of claim 2 wherein, in an unselected block, all pass transistors to wordlines are gated off after a voltage less than the unselect voltage is applied to each pass transistor and the wordlines float to prevent erasure.
4 . The method of claim 3 wherein the unselect voltage is closer to the voltage applied to the substrate than to the select voltage.
5 . A nonvolatile memory comprising:
a memory array comprising plural strings of memory cells on a substrate and wordlines across the strings to pages of memory cells;
a pass transistor to each wordline;
a block decoder that enables each pass transistor in a selected block during an erase operation;
a substrate voltage source that applies an erase voltage to the substrate during the erase operation; and
a wordline decoder that applies a common select voltage to each pass transistor of a page to be erased in the selected block and a common unselect voltage to each wordline of each other page in the selected block, the wordline decoder responding to address instructions to apply the select voltage to plural wordlines of the selected block and to apply the unselect voltage to plural wordlines of the selected block.
6 . The nonvolatile memory of claim 5 wherein:
the wordline decoder is adapted to apply the select voltage to any of the wordlines and the unselect voltage to any of the wordlines;
a resulting voltage of each selected wordline is substantially the same as the select voltage and a resulting voltage of each unselected wordline is substantially the same as the unselect voltage or a floating voltage coupled from the unselect voltage toward the erase voltage.
7 . The nonvolatile memory of claim 6 wherein, in an unselected block, all pass transistors to wordlines are gated off after a voltage less than the unselect voltage is applied to each pass transistor and the wordlines float to prevent erasure.
8 . The nonvolatile memory of claim 7 wherein the unselect voltage is closer to the erase voltage applied to the substrate than to the select voltage.
9 . A nonvolatile memory comprising:
a memory array comprising plural strings of memory cells on a substrate and wordlines across the strings to pages of memory cells;
a pass transistor to each wordline;
a block decoder that enables each pass transistor in a selected block during an erase operation;
a substrate voltage source that applies an erase voltage to the substrate during the erase operation; and
a wordline decoder that applies a select voltage to each pass transistors of a page to be erased in the selected block and an unselect voltage to each wordline of each other page in the selected block, the unselect voltage being closer to the erase voltage than to the select voltage.
10 . The nonvolatile memory of claim 9 wherein the wordline decoder is adapted to apply the select voltage to any of the wordlines and the unselect voltage to any of the wordlines.
11 . The nonvolatile memory of claim 9 wherein a resulting voltage of each selected wordline is substantially the same as the select voltage and a resulting voltage of each unselected wordline is substantially the same as the unselect voltage.
12 . The nonvolatile memory of claim 9 wherein the select voltage is about zero volts and the unselect voltage is about equal to the voltage.
13 . The nonvolatile memory of claim 9 wherein a resulting voltage of each selected wordline is substantially the same as the select voltage and a resulting voltage of each unselected wordline is a floating voltage coupled from the unselect voltage toward the erase voltage.
14 . The nonvolatile memory of claim 13 wherein a common gate signal to each pass transistor of the selected block has a value V 2 , the unselect voltage is greater than V 2 and the unselected wordline precharges to V 2 −Vtn, and wherein V 2 is substantially less than the applied substrate voltage.
15 . The nonvolatile memory of claim 14 wherein V 2 is at least 50% of the erase voltage.
16 . The nonvolatile memory of claim 15 wherein, in an unselected block, all pass transistors to wordlines are gated off after a voltage less than the unselect voltage is applied to each pass transistor and the wordlines float to prevent erasure.
17 . The nonvolatile memory of claim 9 wherein the wordline decoder is adapted to apply a select voltage to each pass transistor of any page to be erased in the selected block and a common unselect voltage to any wordline of each other page in the selected block, the wordline decoder responding to address instructions to apply the select voltage to plural wordlines of the selected block and to apply the unselect voltage to plural wordlines of the selected block.
18 . The nonvolatile memory of claim 17 wherein a resulting voltage of each selected wordline is substantially the same as the select voltage and a resulting voltage of each unselected wordline is substantially the same as the unselect voltage.
19 . The nonvolatile memory of claim 9 further comprising sensors configured to sense state of strings of the selected block.
20 . The nonvolatile memory of claim 19 wherein each string is connected to an end voltage, the level of the end voltage being selected from one of plural voltage levels dependent on the number of selected word lines.