ASYNCHRONOUS BRIDGE CHIP
A memory device multi-chip package containing conventional parallel bus flash memory dies interfacing to an external parallel bus having the same format and protocol. A bridge chip within the memory device interfaces internally over one or more internal parallel bus interfaces to the flash dies within the package. The bridge chip presents a single load on the external bus interface so that several memory device multi-chip packages (MCPs) can be connected to a controller, thereby increasing the number of flash dies supported by a single controller channel operating at full performance.
1 . A memory device, comprising:
a plurality of memory devices including first and second memory devices each of the first and second memory devices having an interface configured for a predetermined protocol; and,
a bridge device configured to selectively communicate signals between one of the first and second memory devices, and an external interface configured for the predetermined protocol.
2 . The memory device of claim 1 , wherein the predetermined protocol is a toggle mode NAND flash memory interface protocol.
3 . The memory device of claim 1 , wherein the bridge device enables either the first memory device or the second memory device in response to a chip enable signal received at the external interface.
4 . The memory device of claim 3 , wherein the bridge device includes an internal memory interface configured for the predetermined protocol and coupled to the first memory device.
5 . The memory device of claim 4 , wherein the internal memory interface is a first internal memory interface, and the bridge device includes a second internal memory interface configured for the predetermined protocol and coupled to the second memory device.
6 . The memory device of claim 4 , wherein the second memory device is coupled to the internal memory interface.
7 . The memory device of claim 6 , wherein the internal memory interface is a first internal memory interface, and the bridge device includes a second internal memory interface configured for the predetermined protocol and coupled to at least one additional memory device configured for the predetermined protocol.
8 . The memory device of claim 1 , wherein the first and second memory devices are memory chips, and the bridge device is a bridge chip, and the memory chips and the bridge chip are integrated in a multi-chip package (MCP).
9 . The memory device of claim 8 , wherein the MCP includes pins coupled to the external interface.
10 . The memory device of claim 1 , wherein the bridge device includes a first internal memory interface and a second internal memory interface.
11 . The memory device of claim 10 , wherein the bridge device includes a routing controller configured to selectively couple the signals between the external interface and either the first internal memory interface or the second internal memory interface in response to memory select signals.
12 . The memory device of claim 11 , wherein the signals include control signals and data signals.
13 . The memory device of claim 12 , wherein the bridge device includes a control signal router configured to couple the control signals received at the external interface to either the first internal memory interface or the second internal memory interface in response to memory select signals.
14 . The memory device of claim 13 , wherein the bridge device further includes a data router configured to
couple read data from either the first internal memory interface or the second internal memory interface to the external interface in a read operation, or
couple write data from the external interface to either the first internal memory interface or the second internal memory interface in a write operation, in response to the memory select signals.
15 . The memory device of claim 14 , wherein the data router includes bi-directional signal paths, where a first signal path transfers read data from either the first internal memory interface or the second internal memory interface to the external interface, and a second signal path transfers write data from the external interface to either the first internal memory interface or the second internal memory interface.
16 . The memory device of claim 15 , wherein the bridge device further includes a command decoder configured to enable the first signal path in response to a received read command or to enable the second signal path in response to a received write command.
17 . The memory device of claim 11 , wherein the memory select signals include chip enable signals received at the external interface, and the routing controller includes circuitry for passing one of the chip enable signals to each of the first and the second memory devices.
18 . The memory device of claim 11 , wherein the memory select signals include memory address signals received at the external interface, and the routing controller includes an address decoder for decoding the memory address signals into chip enable signals, and for providing one of the chip enable signals to each of the first and the second memory devices.
19 . A memory system, comprising:
a memory controller connected to a memory bus for the communication of signals according to a predetermined protocol;
a multi-chip package containing
a plurality of memory chips including at least two memory chips, each of the chips having a memory interface configured for the predetermined protocol; and,
a bridge chip having an external interface configured for the predetermined protocol and coupled to the memory bus, and at least one internal memory interface coupled to the at least two memory chips for transferring the signals between a selected memory chip of the at least two memory chips and the external interface, the external interface presenting a single load on the memory bus.
20 . The memory system of claim 19 , wherein each internal memory interface is coupled to only one of the at least two memory chips.
21 . The memory system of claim 19 , wherein a plurality of memory chips are connected in parallel to each internal memory interface.