Granted Patent B2

US 8,060,730 · App. 12/130,012 · Granted Nov 15, 2011

Abstract

Claims (49)

1. In a data processing system, a method comprising:

providing a plurality of test points located at predetermined circuit nodes;

executing test code which includes a set of software-controllable interrupts;

during execution of the test code, using a multiple input shift register (MISR) to accumulate data values from the plurality of test points to generate a MISR signature;

determining one or more selected software-controllable interrupt types; and

during execution of the test code, using the MISR to also accumulate data values from the plurality of test points during exception processing of one or more software-controllable interrupts within the set of software-controllable interrupts which are of the one or more selected software-controllable interrupt types to generate the MISR signature.

2. The method of claim 1 , further comprising:

during execution of the test code, receiving an asynchronous exception; and

disabling the MISR when processing the asynchronous exception.

3. The method of claim 1 , further comprising:

providing a test control register having a plurality of fields, each of the plurality of fields for selecting or not selecting a corresponding software-controllable interrupt type.

4. The method of claim 3 , wherein determining the one or more selected software-controllable interrupt types comprises using the test control register to determine the one or more selected software-controllable interrupt types.

5. The method of claim 1 , further comprising:

during execution of the test code, disabling the MISR from accumulating data values during exception processing of one or more of the software-controllable interrupts within the set of software-controllable interrupts which are not of the one or more selected software-controllable interrupt types.

6. The method of claim 1 , wherein exception processing of the one or more of the software-controllable interrupts within the set of software-controllable interrupts which are of the one or more selected software-controllable interrupt types comprises executing a corresponding exception handler in response to detecting an exception caused by the one or more of the software-controllable interrupts, and wherein during the exception processing, the MISR is used to accumulate data values during at least one clock cycle which occurs after detecting the exception and prior to executing an initial instruction of the corresponding exception handler.

7. The method of claim 1 , wherein during exception processing of the one or more of the software-controllable interrupts within the set of software-controllable interrupts which are of the one or more selected software-controllable interrupt types, the MISR is used to accumulate data values during one or more clock cycles which are not associated with a writeback stage of an instruction pipeline of the data processing system.

8. The method of claim 7 , wherein, when not exception processing, using the MISR to accumulate data values from the plurality of test points to generate the MISR signature comprises updating the MISR during a writeback stage of an instruction pipeline of the data processing system.

9. The method of claim 1 , further comprising:

executing the test code which includes the set of software-controllable interrupts a second time;

during execution of the test code the second time, using the MISR to accumulate data values from the plurality of test points to generate a second MISR signature;

during execution of the test code the second time, using the MISR to also accumulate data values from the plurality of test points during exception processing of one or more of the software-controllable interrupts within the set of software-controllable interrupts which are of the one or more selected software-controllable interrupt types to generate the second MISR signature; and

comparing the second MISR signature to the MISR signature to determine if a test error has occurred.

10. A data processing system, comprising:

a multiple input shift register (MISR) which accumulates data values from a plurality of test points located at predetermined circuit nodes to generate a MISR signature;

test control storage circuitry which indicates one or more selected software-controllable interrupt types; and

processing circuitry which executes processor instructions, wherein the processing circuitry executes test code which includes a set of software-controllable interrupts, wherein during execution of the test code, the MISR accumulates data values from the plurality of test points during exception processing of one or more of the software-controllable interrupts within the set of software-controllable interrupts which are of the one or more selected software-controllable interrupt types to generate the MISR signature.

11. The data processing system of claim 10 , further comprising:

MISR control logic coupled to the MISR, wherein the MISR control logic disables the MISR during processing of a received asynchronous exception.

12. The data processing system of 10 , further comprising:

exception logic which, in response to detecting an exception, performs a plurality of internal operations during exception processing, wherein during the exception processing of the one or more of the software-controllable interrupts within the set of software-controllable interrupts which are of the one or more selected software-controllable interrupt types, the MISR accumulates data values from the plurality of test points during one or more of the plurality of internal operations.

13. The data processing system of claim 12 , wherein the processing circuitry implements an instruction pipeline having a writeback stage, and wherein during the exception processing of the one or more of the software-controllable interrupts within the software-controllable interrupts which are of the one or more selected software-controllable interrupt types, the MISR does not accumulate data values from the plurality of test points during the writeback stage.

14. The data processing system of claim 13 , wherein the processing circuitry, when not exception processing, uses the MISR to accumulate data values from the plurality of test points to generate the MISR signature by updating the MISR during the writeback stage.

15. In a data processing system, a method comprising:

providing a plurality of test points located at predetermined circuit nodes;

executing test code which includes a set of software-controllable interrupts, each software-controllable interrupt having a corresponding exception handler;

during execution of the test code, using a multiple input shift register (MISR) to accumulate data values from the plurality of test points to generate a MISR signature;

in response to executing a first software-controllable interrupt of the set of software-controllable interrupts, generating an exception; and

in response to detecting the exception, performing at least one operation prior to executing an initial instruction of a first exception handler corresponding to the first software-controllable interrupt, wherein the MISR is also used to accumulate data values from the plurality of test points to generate the MISR signature during the at least one operation.

16. The method of claim 15 , wherein the at least one operation comprises

saving current context information.

17. The method of claim 16 , wherein the at least one operation further

comprises generating a new program counter value for use in execution of the initial instruction of the first exception handler, and wherein the MISR is used to accumulate data values from the plurality of test points to generate the MISR signature when saving current context information and when generating the new program counter value.

18. The method of claim 15 , wherein using the MISR to also accumulate data values from the plurality of test points to generate the MISR signature during the at least one operation further comprises:

determining one or more selected software-controllable interrupt types; and

using the MISR to accumulate data values from the plurality of test points to generate the MISR signature during the at least one operation when the first software-controllable interrupt is of the one or more selected software-controllable interrupt types.

19. The method of claim 18 , further comprising:

disabling the MISR from accumulating data values during exception processing of the first software-controllable interrupt when the first software-controllable interrupt is of the one or more selected software-controllable interrupt types and when other operations other than the at least one operation are being performed.

20. The method of claim 15 , further comprising:

disabling the MISR from accumulating data values during exception processing of the first software-controllable interrupt when other operations other than the at least one operation are being performed.

Assignments (14)