Delay Locked Loop Implementation In A Synchronous Dynamic Random Access Memory
A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.
1 . A synchronous memory comprising:
a clock input signal; and
a delay locked loop (DLL) having an adjustable delay line for generating a driving clock signal from the clock input signal, the adjustable delay line being a tapped delay line and the DLL being enabled and disabled by external control.
2 . Synchronous memory as claimed in claim 1 wherein taps provide plural outputs of the delay line.
3 . Synchronous memory as claimed in claim 2 wherein a comparator in the DLL determines one of the tap outputs that forms the driving clock signal.
4 . A synchronous memory comprising:
a clock input signal;
a delay locked loop (DLL) having an adjustable delay line for generating a driving clock signal from the clock input signal, the DLL being enabled and disabled by external control, and
a data output buffer enabled by the driving clock signal for outputting data to an output terminal.
5 . A method of providing a clock to a synchronous memory comprising:
generating a driving clock signal from a clock input signal through a delay locked loop (DLL) having an adjustable delay line, the adjustable delay line being a tapped delay line; and
using external control, disabling the delay locked loop.
6 . The method of claim 5 wherein taps provide plural outputs of the delay line.
7 . The method of claim 6 wherein one of the tap outputs is determined by a comparator in the DLL to form the driving clock signal.