Gate electrode for semiconductor devices
The present invention provides an MIS type semiconductor device, comprising a semiconductor substrate and a gate electrode formed on the gate insulating film and formed of gate material. The gate electrode comprises: a first layer of activated crystalline gate material having a first side oriented towards a substrate and a second side oriented away from the substrate, the first layer of activated crystalline gate material having a doping level of 10 19 ions/cm 3 or higher, and a second layer of gate material at the second side of the first layer of activated crystalline gate material. The present invention also provides a method for making such a device.
1 . Method of forming a semiconductor device having a gate, comprising:
providing a first layer of amorphous gate material,
doping the first layer of amorphous gate material, thus forming a doped first layer of amorphous gate material,
thermally activating the doped first layer of gate material, thus forming an activated first layer of gate material, and
providing a second layer of gate material on top of the activated first layer of gate material.
2 . A method according to claim 1 , wherein the first and second layers of gate material are silicon-based.
3 . A method according to claim 1 , further comprising patterning the second layer of gate material and the activated first layer of gate material to form one or more gates on the substrate.
4 . A method according to claim 1 , wherein providing a first layer of amorphous gate material includes forming a layer of amorphous gate material having a thickness of about 10 nm to about 40 nm.
5 . A method according to claim 1 , wherein providing a second layer ( 16 ) of gate material includes forming a layer of gate material having a thickness of about 50 nm to about 150 nm.
6 . An MIS type semiconductor device, comprising:
a semiconductor substrate,
a gate electrode formed on the gate insulating film and formed of gate material,
wherein the gate electrode comprises:
a first layer of activated crystalline gate material having a first side oriented towards a substrate and a second side oriented away from the substrate, the first layer of activated crystalline gate material having a doping level of 10 19 ions/cm 3 or higher, and
a second layer of gate material at the second side of the first layer of activated crystalline gate material.
7 . A semiconductor device according to claim 6 , wherein the first layer of activated crystalline gate material has a doping level of about 10 20 ions/cm 3 or higher.
8 . An MIS type semiconductor device according to claim 6 , wherein the doping implant in the activated gate material has an abruptness of about 2 nm or more.
9 . A semiconductor device according to claim 6 , wherein the second layer of gate material consists of amorphous gate material.
10 . A semiconductor device according to claim 6 , wherein the second layer of gate material consists of polycrystalline gate material.
11 . A semiconductor device according to claim 6 , wherein the grain size in the second layer is below about 40 nm.
12 . A semiconductor device according to claim 6 , wherein the first layer is crystalline or very fine-grained, with grains below 5 nm.
13 . A semiconductor device according to claim 6 , wherein a gate insulator is provided between the semiconductor substrate and the gate electrode.
14 . A semiconductor device according to claim 6 , wherein the device is a transistor.
15 . A method according to claim 1 , wherein providing a first layer of amorphous gate material includes forming a layer of amorphous gate material having a thickness of about 20 nm to 30 nm.
16 . A method according to claim 1 , wherein providing a second layer of gate material includes forming a layer of gate material having a thickness of about 70 nm to about 130 nm.
17 . A semiconductor device according to claim 6 , wherein the first layer of activated crystalline gate material has a doping level of about 5×10 20 ions/cm 3 or higher.
18 . An MIS type semiconductor device according to claim 6 , wherein the doping implant in the activated gate material has an abruptness of about 1.5 nm or more.
19 . An MIS type semiconductor device according to claim 6 , wherein the doping implant in the activated gate material has an abruptness of about 1 nm.
20 . A semiconductor device according to claim 6 , wherein the grain size in the second layer is below about 30 nm.