Formation of junctions and silicides with reduced thermal budget
Method of formation of a metal-silicide layer ( 12, 13, 14, 18, 19 ) an a semiconductor substrate ( 1 ), the semiconductor substrate ( 1 ) including at least a dopant region ( 5 ); the dopant region ( 5 ) including an ultra-shallow junction region; the method including as a first step at least one impurity implantation process (IB dopant) for forming the dopant region ( 5 ); the method including as a second step at least one metal implantation process (IB metal) for forming the metal-silicide layer ( 12, 13, 18, 19 ) an the dopant region ( 5 ), and the method including, as a third step carried out after the first and the second step, a low-temperature annealing process wherein simultaneously the dopant region ( 5 ) is activated and the metal-silicide layer ( 12, 13, 14, 18, 19 ) is formed.
1 . Method of manufacturing a semiconductor device comprising the step of forming a metal-silicide layer on a semiconductor substrate,
said semiconductor substrate comprising at least a dopant region;
said dopant region comprising an ultra-shallow junction region;
said method comprising as a first step at least one impurity implantation process for forming said dopant region;
said method comprising as a second step at least one metal implantation process for forming said metal-silicide layer on said dopant region
characterized in that said method is arranged to carry out after said first and said second step:
as a third step a low-temperature annealing process wherein simultaneously said dopant region is activated and said metal-silicide layer is formed.
2 . Method according to claim 1 , wherein said method comprises a pre-amorphisation process by ion beam carried out as an initial process before said first step on at least said dopant region and said conduction region.
3 . Method according to claim 1 , wherein said at least one impurity implantation process comprises a first impurity implantation process using a first impurity to create a junction region of a first conductivity type.
4 . Method according to claim 3 , wherein said at least one impurity implantation process comprises a second impurity implantation process using a second impurity to create a junction region of a second conductivity type.
5 . Method according to claim 3 , wherein said at least one impurity implantation process comprises a second impurity implantation process using said first impurity to create a further junction region of said conductivity type with a different impurity level.
6 . Method according to claim 3 , wherein said at least one metal implantation process for forming said metal-silicide layer comprises a first metal implantation process using a first mask and a first metal to create a first silicide layer on said junction region of said first conductivity type.
7 . Method according to claim 3 , wherein said at least one metal implantation process for forming said metal-silicide layer comprises a second metal implantation process using a second mask and a second metal to create a second silicide layer on said junction region of said second conductivity type.
8 . Method according to claim 3 , wherein said at least one metal implantation process for forming said metal-silicide layer comprises a further metal implantation process using a further mask and a further metal to create a further silicide layer on said conduction region or said gate conduction region.
9 . Method according to claim 1 , wherein said method comprises in said second step said at least one metal implantation process for forming said metal-silicide layer on a conduction region.
10 . Method according to claim 1 wherein said method comprises in said second step said at least one metal implantation process for forming said metal-silicide layer on a gate conduction region of a gate.
11 . Method according to claim 1 , wherein said low annealing temperature process is a solid-phase epitaxial regrowth process.
12 . Method according to claim 1 , wherein each of said first, second, or further metal is capable of forming a metal-di-silicide compound during said low temperature annealing process.
13 . Method according to claim 1 , wherein said metal silicide layer is formed as at least one of a metal silicide layer adjacent to another structural element arranged within said junction region, or a remote metal silicide layer in said junction region remote from said other structural element, and a single metal silicide layer in said conduction region outside of said junction region.
14 . Semiconductor device on semiconductor substrate comprising at least a dopant region, said dopant region comprising an ultra-shallow junction region, wherein said semiconductor device is manufactured by a method of formation of a metal-silicide layer in accordance with claim 1.