IP Library Granted Patent US 9,530,857
Granted Patent B2
US 9,530,857 · App. 10/560,717 · Granted Dec 27, 2016

Electronic device, assembly and methods of manufacturing an electronic device including a vertical trench capacitor and a vertical interconnect

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Quick Facts
Patent No.
US 9,530,857
App. No.
10/560,717
Granted
Dec 27, 2016
Kind
B2
Abstract

A semiconductor substrate comprises both vertical interconnects and vertical capacitors with a common dielectric layer. The substrate can be suitably combined with further devices to form an assembly. The substrate can be made in etching treatments including a first step on the one side, and then a second step on the other side of the substrate.

Claims (16)

1. An electronic device comprising a semiconductor substrate having a first side and a second side; a vertical trench capacitor on the first side of the substrate, the vertical trench capacitor including a plurality of trenches in which dielectric material is present between first and second conductive surfaces; a vertical interconnect that extends through the substrate from the first side to the second side, the vertical interconnect being insulated from the substrate by dielectric material, the dielectric material of the vertical interconnect and the dielectric material of the vertical trench capacitor being a common material formed from a single deposition layer; wherein the substrate comprises a high-ohmic zone which is present adjacent to the vertical capacitors and acts as a protection against parasitic currents; and a planar capacitor on the first side of the substrate, the planar capacitor including dielectric material formed from the common material of the single deposition layer, and wherein the high-ohmic zone separates the planar capacitor from the vertical trench capacitor.

2. The electronic device as claimed in claim 1 , wherein the vertical interconnect includes a plurality of parallel trenches each of which is substantially filled with an electrically conductive material, the dielectric material of the vertical interconnect being in direct contact with the semiconductor substrate in which the vertical trench capacitor is formed, along a sidewall of the vertical interconnect.

3. The electronic device as claimed in claim 1 , wherein

contact pads for coupling to an external carrier are present on the second side;

a first vertical interconnect is used for grounding and

a second vertical interconnect is used for signal transmission.

4. The electronic device as claimed in claim 3 , wherein the first and second vertical interconnects are designed so as to form a coaxial structure.

5. An assembly comprising the electronic device of claim 1 , and a semiconductor device, where the semiconductor device is electrically connected to bond pads present on the first side of the substrate.

6. The electronic device as claimed in claim 1 , wherein the dielectric material of the vertical trench capacitor and the dielectric material of the vertical interconnect are formed by depositing a layer of dielectric material on the substrate and partially etching the deposited layer of dielectric material.

7. The electronic device as claimed in claim 1 , wherein the vertical interconnect is substantially filled with a conductive material, the conductive material of the vertical interconnect and the second conductive surface of the vertical trench capacitor being formed from a common material of a single deposition layer of conductive material.

8. An electronic device comprising:

a semiconductor substrate having a first side and a second side;

a vertical trench capacitor on the first side of the substrate, the vertical trench capacitor including a plurality of trenches in which a dielectric material is present between first and second conductive surfaces; and

a vertical interconnect that extends through the substrate from the first side to the second side, the vertical interconnect being insulated from the substrate by a dielectric material, the dielectric material of the vertical interconnect and the dielectric material of the vertical trench capacitor being a common material formed from a single deposition layer, the vertical interconnect having a first part and a second part, where the first part is exposed on the first side of the substrate, is narrower than the second part and has a substantially cylindrical shape.

9. The electronic device as claimed in claim 8 , wherein the first part of the vertical interconnect comprises a plurality of parallel through-holes that extend from the first side of the substrate to the second part of the vertical interconnect, each of the plurality of parallel through-holes being substantially filled with an electrically conductive material.

10. An electronic device comprising: a semiconductor substrate having a first side and a second side; a vertical trench capacitor on the first side of the substrate, the vertical trench capacitor including a plurality of trenches in which dielectric material is present between first and second conductive surfaces; and a vertical interconnect that extends through the substrate from the first side to the second side, the vertical interconnect being insulated from the substrate by dielectric material, the dielectric material of the vertical interconnect and the dielectric material of the vertical trench capacitor being common material formed from a single deposition layer, wherein the dielectric material extends over surfaces on both the first side and second side of the substrate.

Assignments (7)
CHANGE OF NAME Recorded Nov 19, 2025
From: TESSERA ADVANCED TECHNOLOGIES, INC.
To: ADEIA SEMICONDUCTOR ADVANCED TECHNOLOGIES INC.
Reel/Frame 073635/0304 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 8, 2014
From: NXP B.V.
To: TESSERA ADVANCED TECHNOLOGIES, INC.
Reel/Frame 032626/0262 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2007
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: NXP B.V.
Reel/Frame 019719/0843 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2005
From: ROOZEBOOM, FREDDY; BUIJSMAN, ADRIANUS ALPHONSUS JOZEF; GAMAND, PATRICE; KEMMEREN, ANTONIUS LUCIEN ADRIANUS MARIA; HUBERT, GERARDUS TARCISIUS MARIA
To: KONINKLIJKE PHILIPS ELECTRONICS, N.V.
Reel/Frame 017376/0982 →