Lateral field-effect transistor having an insulated trench gate electrode
View Patent ↗A field-effect transistor having cells ( 18 ) each having a source region ( 22 ), source body region ( 26 ), drift region ( 20 ), drain body region ( 28 ) and drain region ( 24 ) arranged longitudinally, laterally alternating with structures to achieve a reduced surface field. In embodiments, the structures can include longitudinally spaced insulated gate trenches ( 35 ) defining a gate region ( 31 ) adjacent the source or drain region ( 22, 24 ) and a longitudinally extending potential plate region ( 33 ) adjacent the drift region ( 20 ). Alternatively, a separate potential plate region ( 33 ) or a longitudinally extending semi-insulating field plate ( 50 ) may be provided adjacent the drift region ( 20 ). The transistor is suitable for bi-directional switching.
1. A semiconductor device having a first major surface comprising: at least one cell having longitudinally spaced source and drain regions at the first major surface, a source body region at the end of the source region facing the drain region, a drain body region at the end of the drain region facing the source region and a drift region extending from the source body region to the drain body region;
at least one pair of longitudinally spaced insulated gates, one of the pair being adjacent to the source body region and the other of the pair being adjacent to the drain body region, the gates extending longitudinally with longitudinal side walls, the insulated gates being formed in trenches having gate dielectric along the side and end walls and the base of the trench and a gate conductor within the gate dielectric; and
plates adjacent to the drift region for controlling the drift region to carry current flowing between source and drain when the device is switched on and to support a voltage between source and drain when the device is switched off.
2. A semiconductor device according to claim 1 wherein the source and drain regions are of a first conductivity type and the source and drain body regions are of a second conductivity type opposite to the first conductivity type.
3. A semiconductor device according to claim 2 wherein the drift region is of the first conductivity type with a dopant concentration in the range of 5×10 16 cm −3 to 5×10 17 cm −3 .
4. A semiconductor device according to claim 1 wherein the plates are insulated conductive potential plates adjacent to the drift region.
5. A semiconductor device according to claim 4 wherein an insulated conductive potential plate extends from the each of the pair of gates longitudinally towards the other of the pair of gates adjacent to the drift region, each conductive potential plate being in electrical contact with the gate from which it extends.
6. A semiconductor device according to claim 5 wherein the dielectric along the side wall of the potential plates has a greater thickness than the dielectric along the side wall of the gates.
7. A semiconductor device according to claim 4 comprising at least one longitudinally extending potential plate between the longitudinally spaced gates and insulated from the longitudinally spaced gates.
8. A semiconductor device according to claim 1 comprising a plurality of cells spaced laterally across the first major surface of the substrate alternating with pairs of longitudinally spaced insulated gates.
9. A semiconductor device according to claim 1 wherein the plates comprise resistive field plates extending longitudinally on either side of each cell from a source end adjacent to the source to a drain end adjacent to the drain.
10. A semiconductor device according to claim 9 further comprising a source contact connected in common to the source region or regions and to the source end of the field plate or plates and a drain contact connected in common to the drain region or regions and drain end the field plate or plates.
11. A semiconductor device according to claim 9 wherein the gate trenches extend from the first major surface to the substrate and the semi-insulating field plates each extend from the first major surface to the substrate.
12. A semiconductor device according to claim 9 including a plurality of cells and field plates alternating laterally across the first major surface.
13. A semiconductor device according to claim 1 wherein the gates are arranged within the lateral bounds of each cell.
14. A semiconductor device according to claim 1 wherein the source body region extends under the source region and the drain body region extends under the drain region.
15. A semiconductor device according to claim 1 comprising a source contact connected in common to the source and to the source body region and a drain contact connected in common to the drain and the drain body region.