Delay time correction circuit, video data processing circuit, and flat display device
The present invention is applied to, for example, a liquid crystal display device having a driving circuit integrally formed on an insulating substrate, and makes it possible to effectively avoid a variation in delay time in a logical circuit using TFTs or the like by inserting dummy data (DD) into input data (D 1 ) and forcedly switching the logical level of the input data (D 1 ) at a predetermined timing during a quiescent period (T 2 ) in which the input data is held at a constant logical level.
1 . A delay time correction circuit, characterized by inserting, for a data processing circuit for processing input data having a quiescent period during which the input data is held at a constant logical level for a constant period at a constant cycle, dummy data having a logical level opposite to the constant logical level into the input data at a predetermined timing during the quiescent period.
2 . A data processing circuit for processing input data having a quiescent period during which the input data is held at a constant logical level for a constant period at a constant cycle, characterized by inserting dummy data having a logical level opposite to the constant logical level into the input data at a predetermined timing during the quiescent period.
3 . The data processing circuit according to claim 2 , characterized in that:
the input data is video data; and
the quiescent period is a horizontal blanking period or a vertical blanking period.
4 . A flat display device comprising:
a display section having pixels arranged in a matrix form;
a vertical driving circuit for sequentially selecting pixels of the display section through gate lines; and
a horizontal driving circuit for converting gradation data indicative of gradations of the pixels into analog signals by sequentially sampling the gradation data, and driving the pixels selected through the gate lines by driving signal lines of the display section by the analog signals, characterized in that the gradation data is processed by inserting dummy data having a logical level opposite to a logical level during a horizontal blanking period into the gradation data at a predetermined timing during the horizontal blanking period of the gradation data.
5 . The flat display device according to claim 4 , characterized in that an active devices for processing the gradation data is formed by low-temperature polysilicon.
6 . The flat display device according to claim 4 , characterized in that an active devices for processing the gradation data is formed by CGS.