Method for the production of a plurality of optoelectronic semiconductor chips and optoelectronic semiconductor chip
View Patent ↗A method for the production of a plurality of optoelectronic semiconductor chips each having a plurality of structural elements with respectively at least one semiconductor layer. The method involves providing a chip composite base having a substrate and a growth surface. A non-closed mask material layer is grown onto the growth surface in such a way that the mask material layer has a plurality of statistically distributed windows having varying forms and/or opening areas, a mask material being chosen in such a way that a semiconductor material of the semiconductor layer that is to be grown in a later method step essentially cannot grow on said mask material or can grow in a substantially worse manner in comparison with the growth surface. Subsequently, semiconductor layers are deposited essentially simultaneously onto regions of the growth surface that lie within the windows. A further method step is singulation of the chip composite base with applied material to form semiconductor chips. An optoelectronic semiconductor component is produced according to the method.
1. A method for the production of a plurality of optoelectronic semiconductor chips each having a plurality of structural elements with respectively at least one semiconductor layer, the method comprising the steps of:
providing a chip composite base having a substrate and a growth surface;
growing a non-closed mask material layer onto the growth surface in such a way that the mask material layer has a plurality of statistically distributed windows having varying forms and/or opening areas, a mask material being chosen in such a way that a semiconductor material of the semiconductor layer that is to be grown in a later method step essentially cannot grow on said mask material or can grow in a substantially worse manner in comparison with the growth surface;
essentially simultaneously growing semiconductor layers on regions of the growth surface that lie within the windows; and
singulating the chip composite base with applied material to form semiconductor chips each having the plural structural elements arranged alongside one another, the structural elements comprising a semiconductor layer sequence.
2. The method as claimed in claim 1 , in which the chip composite base has at least one semiconductor layer grown epitaxially onto the substrate and the growth surface is a surface on that side of the epitaxially grown semiconductor layer which is remote from the substrate.
3. The method as claimed in claim 1 , in which the chip composite base has a semiconductor layer sequence grown epitaxially onto the substrate with an active zone that emits electromagnetic radiation, and the growth surface is a surface on that side of the semiconductor layer sequence which is remote from the substrate.
4. The method as claimed in claim 1 , in which the structural elements respectively have an epitaxially grown semiconductor layer sequence with an active zone that emits electromagnetic radiation.
5. The method as claimed in claim 1 , in which the mask material has SiO 2 , Si x N y or Al 2 O 3 .
6. The method as claimed in claim 1 , in which, after the growth of the semiconductor layers, a layer made of electrically conductive contact material that is transmissive to an electromagnetic radiation emitted by the active zone is applied to the semiconductor layers, so that semiconductor layers of a plurality of structural elements are electrically conductively connected to one another by the contact material.
7. The method as claimed in claim 1 , in which the average thickness of the mask material layer is less than the cumulated thickness of the semiconductor layers of a structural element.
8. The method as claimed in claim 1 , in which the mask material layer is at least partly removed after the growth of the semiconductor layers.
9. The method as claimed in claim 1 , in which, after the growth of the semiconductor layer sequences, a planarization layer is applied over the growth surface.
10. The method as claimed in claim 9 , in which a material whose refractive index is lower than that of the semiconductor layers is chosen for the planarization layer.
11. The method as claimed in claim 9 , in which a material which has dielectric properties is chosen for the planarization layer.
12. The method as claimed in claim 1 , in which the growth conditions for the growth of the mask material layer are set in such a way that three-dimensional growth is predominant and the mask material layer is predominantly formed from a plurality of three-dimensionally growing crystallites.
13. The method as claimed in claim 1 , in which the growth conditions for the growth of the mask material layer are set in such a way that two-dimensional growth is predominant and the mask material layer is predominantly formed from a plurality of two-dimensionally accreting partial layers.
14. The method as claimed in claim 1 , in which the growth conditions for the growth of the mask material layer are set in such a way that most of the windows are formed with an average propagation of the order of magnitude of micrometers.
15. The method as claimed in claim 1 , in which the growth conditions for the growth of the mask material layer are set in such a way that most of the windows are formed with an average extent of less than or equal to 1 μm.
16. The method as claimed in claim 1 , in which the growth conditions for the growth of the semiconductor layers are set and/or varied during growth in such a way that semiconductor layers of the structural elements at least approximately define a curved form.
17. The method as claimed in claim 1 , in which the mask material layer and the semiconductor layers are grown by means of metal organic vapor phase epitaxy.