Fabrication of single or multiple gate field plates
View Patent ↗A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a field effect transistors. This fabrication process permits a tight control on the field plate operation since dielectric material deposition/growth is typically a well controllable process. Moreover, the dielectric material deposited on the device surface does not need to be removed from the device intrinsic regions: this essentially enables the realization of field-plated devices without the need of low-damage dielectric material dry/wet etches. Using multiple gate field plates also reduces gate resistance by multiple connections, thus improving performances of large periphery and/or sub-micron gate devices.
1. A high electron mobility transistor (HEMT), comprising:
a nucleation layer;
a channel layer on the nucleation layer;
a barrier layer on the channel layer;
a spacer layer on the barrier layer; and
source and drain electrodes making ohmic contacts through the barrier layer such that an electric current flows between the source and drain electrodes when a gate electrode is biased at an appropriate level;
wherein the spacer layer is etched to expose the barrier layer and the gate electrode is deposited such that at least a bottom portion of the gate electrode is on a surface of barrier layer,
wherein a top portion of the gate electrode is patterned to extend across the spacer layer so that the top portion of the gate electrode forms a field plate extending a distance away from the gate electrode towards the drain electrode; and
wherein a passivation layer covers both the gate electrode and at least a portion of the spacer layer.
2. The HEMT of claim 1 , wherein the electric current flows between the source and drain electrodes via a two-dimensional electron gas (2DEG) induced at a heterointerface between the channel layer and barrier layer when the gate electrode is biased at the appropriate level.
3. The HEMT of claim 1 , wherein the portion of the gate electrode on the spacer layer forms an epitaxial field plate.
4. The HEMT of claim 1 , wherein the spacer layer comprises a dielectric layer, a layer of undoped or depleted Al x Ga 1−x N (0<=x<=1) material, or a combination thereof.
5. The HEMT of claim 1 , wherein the field plate is formed above the spacer layer and extends a distance Lf (field plate distance) from an edge of the gate electrode towards the drain electrode.
6. The HEMT of claim 1 , wherein the field plate is electrically connected to the gate electrode.
7. The HEMT of claim 1 , wherein the field plate is formed during the same deposition step as an extension of the gate electrode.
8. The HEMT of claim 1 , wherein the field plate and gate electrode are formed during separate deposition steps.
9. The HEMT of claim 1 , wherein the substrate comprises silicon carbide, sapphire, spinel, zinc oxide, silicon or any other material capable of supporting growth of Group III-nitride materials.
10. The HEMT of claim 1 , wherein the nucleation layer is an Al z Ga 1−z N (0<=z<=1) nucleation layer.
11. The HEMT of claim 1 , wherein the nucleation layer is an AlN nucleation layer.
12. The HEMT of claim 1 , wherein the channel layer is a high resistivity Group III-nitride channel layer.
13. The HEMT of claim 1 , wherein the channel layer comprises Al x Ga y In( 1−x−y )N (0<=x<=1, 0<=y<=1, x+y<=1).
14. The HEMT of claim 1 , wherein the channel layer comprises GaN:Fe.
15. The HEMT of claim 1 , wherein the barrier layer comprises Al x Ga 1−x N (0<=x<=1).
16. The HEMT of claim 1 , wherein the barrier layer comprises AlN and AlGaN.
17. The HEMT of claim 1 , wherein each of the channel layer and barrier layer comprise sub-layers that are doped or undoped layers of Group III-nitride materials.
18. The HEMT of claim 1 , wherein the spacer layer is a Group III-nitride semiconductor spacer layer grown on the barrier layer that is an Al x Ga 1−x N barrier layer.
19. The HEMT of claim 1 , wherein the spacer layer has a uniform composition.
20. The HEMT of claim 1 , wherein the spacer layer has a graded composition.
21. The HEMT of claim 1 , wherein the spacer layer is undoped.
22. The HEMT of claim 1 , wherein the spacer layer is fully depleted as grown.
23. The HEMT of claim 1 , wherein the gate electrode is formed after formation of the barrier layer, a passivation layer is deposited on the device, and the field plate is then formed on the passivation layer overlapping the gate and extending a distance Lf in a gate-drain region, and the passivation layer serves as the spacer layer for the field plate.