IP Library Granted Patent US 7,696,599
Granted Patent B2
US 7,696,599 · App. 10/580,619 · Granted Apr 13, 2010

Trench MOSFET

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Quick Facts
Patent No.
US 7,696,599
App. No.
10/580,619
Granted
Apr 13, 2010
Kind
B2
Abstract

A trench MOSFET with drain ( 8 ), drift region ( 10 ) body ( 12 ) and source ( 14 ). In order to improve the figure of merit for use of the MOSFET as control and sync FETs, the trench ( 20 ) is partially filled with dielectric ( 24 ) adjacent to the drift region ( 10 ) and a graded doping profile is used in the drift region ( 10 ).

Claims (22)

1. An insulated gate field effect transistor, comprising:

a source region of a first conductivity type;

a body region of a second conductivity type opposite to the first conductivity type adjacent to the source region;

a drift region of exclusively the first conductivity type adjacent to the body region;

a drain region of the first conductivity type adjacent to the drift region, so that body and drift regions are arranged between the source and drain regions, the drain region being of higher doping density than the drift region, and wherein the region between the body region and the drain region is made up of exclusively the drift region of exclusively the first conductivity type; and

insulated trenches extending from the source region through the body region and into the drift region, each trench having sidewalls, and including an insulator on the sidewalls, and a conductive gate electrode between the insulating sidewall,

wherein the base of each trench is filled with an insulator plug adjacent to substantially all of the length of the drift region between the body region and drain region, and the respective gate electrode is provided in the trench over the plug adjacent to the source and body regions.

2. An insulated gate field effect transistor according to claim 1 wherein the doping concentration in the body region is in the range of about 0.5×10 17 cm −3 to about 3×10 17 cm −3 , and the doping concentration in the drift region is in the range of about 0.5×10 15 cm −3 to about 2×10 17 cm −3 .

3. An insulated gate field effect transistor according to claim 1 wherein the plug is of dielectric filler filling the trench between the insulator on the sidewalls adjacent to the drain region.

4. An insulated gate field effect transistor according to claim 1 having a semiconductor body having opposed first second major surfaces,

wherein the source region is at the first major surface over the body region, the body region is over the drift region and the drift region is over the drain region, and

the trench extends from the first major surface towards the second major surface through the source, body and drift regions.

5. An insulated gate field effect transistor according to claim 4 having a plurality of cells, each cell having a source region at centre of the cell surrounded by the insulated trench.

6. An insulated gate field effect transistor according to claim 5 wherein the cells have a hexagonal geometry.

7. An insulated gate field effect transistor according to claim 5 wherein the trench has gate oxide on the sidewalls, and the trench adjacent to the drift region is filled with filler oxide between the gate oxide on the sidewalls on either side of the trench.

8. An insulated gate field effect transistor according to claim 4 having a plurality of cells, arranged as stripes across the first major surface with alternating trenches and source regions.

9. An insulated gate field effect transistor according to claim 5 wherein the cell pitch is in the range of about 0.2 microns to about 0.7 microns.

10. An insulated gate field effect transistor according to claim 1 wherein the doping concentration in the drift region is non-uniform.

11. An insulated gate field effect transistor according to claim 10 wherein the non-uniform doping concentration in the drift region comprises a higher doping concentration adjacent to the drain region and a lower doping concentration adjacent to the body region.

12. An insulated gate field effect transistor according to claim 11 wherein the non-uniform doping concentration in the drift region is linearly graded from the higher doping concentration adjacent to the drain region to the lower doping concentration adjacent to the body region.

13. An insulated gate field effect transistor according to claim 10 wherein the doping concentration in the body region is in the range of about 0.5×10 17 cm −3 to about 3×10 17 cm −3 , and the doping concentration in the drift region is in the range of about 1×10 15 cm −3 to about 2×10 cm −3 .

14. An insulated gate field effect transistor according to claim 1 wherein the trench extends through the source region, the body region, and the drift region toward the drain region, without entering the drain region.

Assignments (13)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 13, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 048328/0964 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 8, 2016
From: NXP B.V.
To: NEXPERIA B.V.
Reel/Frame 039610/0734 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2007
From: KONINKLIJKE PHILIPS ELECTRONICS N.V.
To: NXP B.V.
Reel/Frame 019719/0843 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 24, 2006
From: HUETING, RAYMOND; HIJZEN, ERWIN A.
To: KONINKLIJKE PHILIPS ELECTRONICS N.V.
Reel/Frame 017960/0420 →