Load-aware circuit arrangement
The present invention relates to a circuit arrangement and method of controlling power consumption of the circuit arrangement, wherein a load applied at a circuit component is determined and the drive capacity of the circuit component is adjusted responsive to the determination result. In particular, the circuit component is tailored to have just sufficient drive capacity depending on the potential load which may be determined by examining a configuration information loaded to the circuit arrangement. Tailoring for sufficient drive can be achieved either by varying the size or number of circuit components or by adjusting the threshold voltage of circuit elements, or by doing both. Thereby, power consumption can be reduced when circuit components are driven at loads lower than the worst case load.
1. A configurable circuit arrangement comprising at least one circuit component at which a load is applied that can vary during operation of said circuit arrangement, wherein said configurable circuit arrangement comprises:
load determination means for determining a load applied at said at least one circuit component having different fan-in or fan-out depending on a configuration of said configurable circuit arrangement; and
adjusting means for switching off a buffer connected to the at least one circuit component according to the determination of the applied load, wherein switching off the buffer adjusts a drive capacity of said at least one circuit component to a value less than a maximum drive capacity while still meeting a delay specification.
2. A configurable circuit arrangement according to claim 1 , wherein said determination means is configured to determine said load based on a configuration information loaded to said configurable circuit arrangement.
3. A configurable circuit arrangement according to claim 2 , wherein said configuration information comprises a configuration bit stream defining at least one of an input load and an output load of said at least one circuit component.
4. A configurable circuit arrangement according to claim 1 , wherein said adjusting means is adapted to generate at least one control signal for simultaneously switching off a section of buffers.
5. A configurable circuit arrangement according to claim 4 , wherein said adjusting means is adapted to derive said control signal from a most significant bit signal of a selection signal obtained from said determination means.
6. A configurable circuit arrangement according to claim 1 , wherein said adjusting means is configured to vary a threshold voltage of circuit elements of said configurable circuit arrangement.
7. A configurable circuit arrangement according to claim 6 , wherein said adjusting means is adapted to change at least one bias voltage responsive to said determination means.
8. A configurable circuit arrangement according to claim 1 , wherein said configurable circuit arrangement is a field programmable gate array device.
9. A configurable circuit arrangement comprising:
at least one circuit component at which a load is applied that can vary during operation of said configurable circuit arrangement;
load determination means for determining a load applied at said at least one circuit component, wherein the at least one circuit component has different fan-in or fan-out depending on a configuration of said configurable circuit arrangement, wherein said determination means is configured to determine said load based on a configuration information loaded to said configurable circuit arrangement, wherein said configuration information is stored in a configuration memory; and
adjusting means for switching off a buffer connected to the at least one circuit component according to the determination of the applied load, wherein switching off the buffer adjusts a drive capacity of said at least one circuit component to a value less than a maximum drive capacity while still meeting a delay specification.
10. A configurable circuit arrangement according to claim 9 , wherein said configuration information comprises a configuration bit stream defining at least one of an input load and an output load of said at least one circuit component.
11. A configurable circuit arrangement according to claim 9 , wherein said adjusting means is adapted to generate at least one control signal for simultaneously switching off a section of buffers.
12. A configurable circuit arrangement according to claim 11 , wherein said adjusting means is adapted to derive said control signal from a most significant bit signal of a selection signal obtained from said determination means.
13. A configurable circuit arrangement according to claim 9 , wherein said adjusting means is configured to vary a threshold voltage of circuit elements of said configurable circuit arrangement.
14. A configurable circuit arrangement according to claim 13 , wherein said adjusting means is adapted to change at least one bias voltage responsive to said determination means.
15. A configurable circuit arrangement according to claim 9 , wherein said configurable circuit arrangement comprises a field programmable gate array device.