MIS-type field-effect transistor
View Patent ↗A strained Si layer 2 is epitaxially grown on a base SiGe layer 1 , and a gate insulating film 3 a and a gate electrode 4 a are formed. An impurity is then ion-implanted (FIG. 2 A) into the base SiGe layer 1 and the strained Si layer 2 using the gate electrode 4 a as a mask, heat treatment is performed for activation, and a source/drain region 6 is formed (FIGS. 2 B and 2 C). In this instance, the film thickness of the strained Si layer 2 is set to 2 T p , where T p (=R p ) is the depth having the maximum concentration of the impurity in the source/drain region 6 of the finished MISFET.
1. An MIS-type field-effect transistor comprising:
a base layer;
a strained active semiconductor layer formed on said base layer;
a gate insulating film formed on said strained active semiconductor layer;
a gate electrode formed on said gate insulating film; and
a source/drain region formed in portions on both sides of said gate electrode inside said strained active semiconductor layer; wherein
an interface between said base layer and said strained active semiconductor layer is at a depth of 2 T p or less from the surface, where T p is the depth of maximum concentration of an impurity introduced for forming said source/drain region.
2. An MIS-type field-effect transistor comprising:
a base layer;
a strained active semiconductor layer formed on said base layer;
a gate insulating film formed on said strained active semiconductor layer;
a gate electrode formed on said gate insulating film;
a source/drain region formed in portions on both sides of said gate electrode inside said strained active semiconductor layer; and
a gate side wall formed on the lateral face of said gate electrode; wherein
a portion of said strained active semiconductor layer under said gate side wall and said gate electrode of said strained active semiconductor layer has a greater film thickness than any other portion of said strained active semiconductor layer; and
an interface between said base layer and said strained active semiconductor layer is at a depth of 2 T p or less from the surface of a region disposed other than under said gate side wall and said gate electrode of said strained active semiconductor layer, where T p is the depth of maximum concentration of an impurity introduced for forming said source/drain region.
3. An MIS-type field-effect transistor comprising:
a base layer;
a strained active semiconductor layer formed on said base layer;
a gate insulating film formed on said strained active semiconductor layer;
a gate electrode formed on said gate insulating layer; and
a built-up layer provided with a source/drain region and formed on said strained active semiconductor layer on both sides of said gate electrode; wherein
said built-up layer has a film thickness of 3 T p or greater, where T p is the depth of maximum concentration of an impurity introduced for forming said source/drain region.
4. The MIS-type field-effect transistor according to claim 3 ,wherein the film thickness of said built-up layer is 5 T p .
5. The MIS-type field-effect transistor according to claim 1 , wherein said base layer is a semiconductor layer having the composition Si 1−x−y Ge x C y (wherein 0 ≦×≦ 1 , 0 ≦y≦ 1 , and 0 <×+y≦ 1 ).
6. The MIS-type field-effect transistor according to claim 1 , wherein said base layer is an Si layer.
7. The MIS-type field-effect transistor according to claim 1 , wherein said base layer is a semiconductor layer, and an insulator layer is formed underneath said base layer.
8. The MIS-type field-effect transistor according to claim 1 , wherein said base layer is an insulator layer.
9. The MIS-type field-effect transistor according to claim 1 , wherein said strained active semiconductor layer is a group IV semiconductor layer.
10. The MIS-type field-effect transistor according to claim 1 , wherein said strained active semiconductor layer is an Si layer.
11. The MIS-type field-effect transistor according to claim 1 , wherein said strained active semiconductor layer is a semiconductor layer having the composition Si 1−x−y Ge x C y (wherein 0 ≦×≦ 1 , 0 ≦y≦ 1 , and 0 ≦×+y ≦ 1 ).
12. The MIS-type field-effect transistor according to claim 11 , further comprising an Si layer with a film thickness of 10 nm or less between said strained active semiconductor layer and said gate insulating film.
13. The MIS-type field-effect transistor according to claim 1 , wherein the MIS-type field effect transistor has a gate length of 0.4 μm or less.
14. The MIS-type field-effect transistor according to claim 1 , wherein said source/drain region is formed by an ion implantation method.
15. The MIS-type field-effect transistor according to claim 1 , wherein said source/drain region is formed by a plasma doping method.
16. The MIS-type field-effect transistor according to claim 1 , wherein said source/drain region is formed by a gas-phase doping method.
17. The MIS-type field-effect transistor according to claim 1 , wherein a portion of said source/drain region near the gate electrode is a region of low impurity concentration.