N-type group III nitride semiconductor layered structure

1. A n-type group III nitride semiconductor layered structure comprising a substrate and, stacked on the substrate, an n-type impurity concentration periodic variation layer comprising an n-type impurity atom higher concentration layer and an n-type impurity atom lower concentration layer, said n-type impurity atom being Ge, pits being provided on a surface of the higher concentration layer (a surface remote from the substrate), and the lower concentration layer being stacked on the higher concentration layer, wherein the higher concentration layer and the lower concentration layer are provided in an alternate and periodic manner, the repetition number of the higher concentration layer and the lower concentration layer is 10 to 1000 and a thickness of a repetition cycle is 1 nm to 1000 nm.

2. The n-type group III nitride semiconductor layered structure according to claim 1 , wherein the number of pits formed is in the range of 1×10 5 /cm 2 to 1×10 10 /cm 2 .

3. The n-type group III nitride semiconductor layered structure according to claim 1 , wherein the flatness (Ra) of the surface of the lower concentration layer (a surface remote from the substrate) is not more m 10 angstroms.

4. The n-type group III nitride semiconductor layered structure according to claim 1 , wherein the thickness of the higher concentration layer and the thickness of the lower concentration layer each are 0.5 to 500 nm.

5. The n-type group III nitride semiconductor layered structure according to claim 1 , wherein the thickness of the lower concentration layer is equal to or larger than the thickness of the higher concentration layer.

6. The n-type group III nitride semiconductor layered structure according to claim 1 , wherein the thickness of the n-type impurity concentration periodic variation layer is 0.1 to 10 μm.

7. The n-type group III nitride semiconductor layered structure according to claim 1 , wherein the concentration of the n-type impurity in the higher concentration layer is 5×10 17 to 5×10 19 cm −3 .

8. The n-type group III nitride semiconductor layered structure according to claim 1 , wherein the concentration of the n-type impurity in the lower concentration layer is lower than the concentration of the n-type impurity in the higher concentration layer and is not more than 2×10 19 cm −3 .

9. The n-type group III nitride semiconductor layered structure according to claim 8 , wherein the n-type impurity is not intentionally doped into the lower concentration layer.

10. The n-type group III nitride semiconductor layered structure according to claim 1 , which comprises a base layer, having a lower carrier concentration than the n-type impurity concentration periodic variation layer, between said substrate and said n-type impurity concentration periodic variation layer.

11. The n-type group III nitride semiconductor layered structure according to claim 10 , wherein said base layer contains an n-type impurity as a dopant and the concentration of the n-type impurity is not more than 5×10 18 cm −3 .

12. The n-type group III nitride semiconductor layered structure according to claim 11 , wherein said base layer is undoped.

13. The n-type group III nitride semiconductor layered structure according to claim 10 , wherein the thickness of the base layer is not less than 1 μm and not than 20 μm.

14. The n-type group III nitride semiconductor layered structure according to claim 13 , wherein the thickness of the base layer is not less than 5 μm and not more than 15 μm.

15. The n-type group III nitride semiconductor layered structure according to claim 10 , wherein the carrier concentration of the base layer is not more than 5×10 17 cm −3 .

16. The n-type group III nitride semiconductor layered structure according to claim 1 , wherein the plane direction of the surface of the substrate is slightly inclined with respect to the just direction.

17. The n-type group III nitride semiconductor layered structure according to claim 16 , wherein the plane direction of the surface of the substrate is inclined by 0.05 to 0.6 degree with respect to the just direction.

18. The n-type group III nitride semiconductor layered structure according to claim 16 wherein said substrate is selected from the group consisting of oxide single crystal materials such as sapphire (α-Al 2 O 3 single crystal), zinc oxide (ZnO), and gallium lithium oxide (LiGaO 2 ), group IV semiconductor single crystals including silicon (Si) single crystals (silicon) and cubic or hexagonal silicon carbide (SiC), and group III-V compound semiconductor single crystals including gallium phosphide (GaP), gallium arsenide (GaAs), and gallium nitride (GaN).

19. A process for producing a n-type group III nitride semiconductor layered structure, which layered structure comprises a substrate and an n-type impurity concentration periodic variation layer stacked on the substrate, the variation layer comprising an n-type impurity atom higher concentration layer and an n-type impurity atom lower concentration layer; wherein said n-type impurity atom is Ge, wherein pits are provided on a surface of the higher concentration layer remote from the substrate, wherein the lower concentration layer is stacked on the higher concentration layer, and wherein the higher concentration layer and the lower concentration layer are provided in an alternate and periodic manner where the repetition number of the higher concentration layer and the lower concentration layer is a number from 10 to 1000 and a thickness of a repetition cycle is 1 nm to 1000 nm,

which process comprises stacking each of the n-type impurity atom higher concentration layer and the n-type impurity atom lower concentration layer so that, in addition to the concentration of the n-type impurity to be doped, conditions for growth within a reactor are also differentiated.

20. The process according to claim 19 wherein conditions for growth of the lower concentration layer are differentiated from conditions for growth of the higher concentration layer so that two-dimensional growth of the layer is accelerated during the growth of the lower concentration layer.

21. The process according to claim 19 , wherein the lower concentration layer is grown at a temperature different from the temperature at which the higher concentration layer is grown.

22. The process according to claim 21 , wherein the lower concentration layer is grown at a temperature above the temperature at which the higher concentration layer is grown.

23. The process according to claim 19 , wherein the lower concentration layer is grown at a pressure different from the pressure at which the higher concentration layer is grown.

24. The process according to claim 23 , wherein the lower concentration layer is grown at a pressure lower than the pressure at which the higher concentration layer is grown.

25. The process according to claim 19 , wherein the carrier gas flow rate in the growth of the lower concentration layer is different from the carrier gas flow rate in the growth of the higher concentration layer.

26. The process according to claim 25 , wherein the carrier gas flow rate in the growth of the lower concentration layer is higher than the carrier gas flow rate in the growth of the higher concentration layer.

27. The process according to claim 19 , wherein the growth speed of the lower concentration layer is different from the growth speed of the higher concentration layer.

28. The process according to claim 27 , wherein the growth speed of the lower concentration layer is lower than the growth speed of the higher concentration layer.

29. The process according to claim 19 , wherein the nitrogen/III ratio in the growth of the lower concentration layer is different from the nitrogen/III ratio in the growth of the higher concentration layer.

30. The process according to claim 29 , wherein the nitrogen/III ratio in the growth of the lower concentration layer is lower than the nitrogen/III ratio in the growth of the n-type impurity atom higher concentration layer.

31. A group III nitride semiconductor light-emitting device comprising a light-emitting layer composed of a group III nitride semiconductor provided on the substrate, wherein the n-type group III nitride semiconductor layered structure according to claim 1 is provided between the substrate and the light-emitting layer.

32. The n-type group III nitride semiconductor layered structure according to claim 17 wherein said substrate is selected from the group consisting of oxide single crystal materials such as sapphire (α-Al 2 O 3 single crystal), zinc oxide (ZnO), and gallium lithium oxide (LiGaO 2 ), group IV semiconductor single crystals including silicon (Si) single crystals (silicon) and cubic or hexagonal silicon carbide (SiC), and group III-V compound semiconductor single crystals including gallium phosphide (GaP), gallium arsenide (GaAs), and gallium nitride (GaN).