IP Library Granted Patent US 7,935,955
Granted Patent B2
US 7,935,955 · App. 10/586,543 · Granted May 3, 2011

Group III nitride semiconductor multilayer structure

Assignee: Showa Denko K.K.
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Quick Facts
Patent No.
US 7,935,955
App. No.
10/586,543
Granted
May 3, 2011
Kind
B2
Abstract

An object of the present invention is to provide a Group III nitride semiconductor multilayer structure having a smooth surface and exhibiting excellent crystallinity, which multilayer structure employs a low-cost substrate that can be easily processed. Another object is to provide a Group III nitride semiconductor light-emitting device comprising the multilayer structure. The inventive Group III nitride semiconductor multilayer structure comprises a substrate; an Al x Ga 1-x N (0≦x≦1) buffer layer which is provided on the substrate and has a columnar or island-like crystal structure; and an Al x In y Ga 1-x-y N (0≦x≦1, 0≦y≦1, 0≦x+y≦1) single-crystal layer provided on the buffer layer, wherein the substrate has, on its surface, non-periodically distributed grooves having an average depth of 0.01 to 5 μm.

Claims (12)

1. A Group III nitride semiconductor multilayer structure comprising a substrate; an Al x Ga 1-x N (0≦x≦1) buffer layer which is provided on the substrate and has a columnar or island-like crystal structure; and an Al x In y Ga 1-x-y N (0≦x≦1, 0≦y≦1, 0≦x+y≦1) single-crystal layer provided on the buffer layer, wherein the substrate has, on its surface, non-periodically distributed scratches having an average depth of 0.01 to 5 μm.

2. A Group III nitride semiconductor multilayer structure according to claim 1 , wherein the grooves have an average depth of 0.1 to 1 μm.

3. A Group III nitride semiconductor multilayer structure according to claim 1 , wherein the substrate is formed of sapphire single crystal or SiC single crystal.

4. A Group III nitride semiconductor multilayer structure according to claim 1 , wherein the buffer layer contains columnar crystal grains.

5. A Group III nitride semiconductor multilayer structure according to claim 1 , wherein the buffer layer has a thickness of 1 to 100 nm.

6. A Group III nitride semiconductor multilayer structure according to claim 1 , wherein the buffer layer is formed through continuously feeding of a Group III element source and a nitrogen source such that the ratio of nitrogen to a Group III element becomes 1,000 or less, or through feeding of merely a Group III element source (in the case where the nitrogen/Group III element ratio is zero).

7. A Group III nitride semiconductor multilayer structure according to claim 1 , wherein the single-crystal layer has a thickness of 1 to 20 μm.

8. A Group III nitride semiconductor multilayer structure according to claim 1 , wherein the single-crystal layer is formed through feeding of a Group III element source and a nitrogen source such that the nitrogen/Group III element ratio becomes 1,600 to 3,200.

9. A Group III nitride semiconductor multilayer structure according to claim 1 , wherein the single-crystal layer is formed while the temperature of the substrate is regulated so as to fall within a range of 1,000 to 1,300° C.

10. A Group III nitride semiconductor multilayer structure according to claim 9 , wherein the temperature of the substrate is regulated so as to fall within a range of 1,050 to 1,200° C.

11. A Group III nitride semiconductor light-emitting device comprising a Group III nitride semiconductor multilayer structure according to claim 1 ; Group III nitride semiconductor layers provided atop the single-crystal layer of the semiconductor multilayer structure, the semiconductor layers including an n-type layer, a light-emitting layer, and a p-type layer; and a negative electrode and a positive electrode which are provided at predetermined positions.

12. A Group III nitride semiconductor light-emitting device according to claim 11 , wherein the n-type layer, the light-emitting layer, and the p-type layer, which constitute the Group III nitride semiconductor layers, are successively provided atop the single-crystal layer in this order; the negative electrode is provided on the n-type layer; and the positive electrode is provided on the p-type layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2012
From: SHOWA DENKO KABUSHIKI KAISHA
To: TOYODA GOSEI CO., LTD.
Reel/Frame 029489/0249 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 19, 2006
From: URASHIMA, YASUHITO
To: SHOWA DENKO K.K.
Reel/Frame 018131/0273 →
Priority Claims (1)
JP 2004-017368 · Jan 26, 2004 · national
Continuity (2)
Provisional Application 60541071 · Feb 3, 2004
Related Publication 20080230780A1 · Sep 25, 2008